XRT74L73
3 CHANNEL, ATM UNI/PPP DS3/E3 FRAMING CONTROLLER
REV. P1.0.1
PRELIMINARY
165
its reading of an ATM cell. Prior to clock edge #2, the
RxFIFO does not contain enough ATM cell data to make
up at least one cell. Hence, the Receive UTOPIA Interface
block negates the RxUClav signal. The ATM Layer pro-
cessor detects that the RxUClav signal has toggled “l(fā)ow”;
at clock edge #2. Hence, the ATM Layer processor will fin-
ish reading in the current ATM cell; from the Receive
UTOPIA Interface block of the UNI (e.g., words W25 and
W26). Afterwards, the ATM Layer processor will negate
the RxUEn signal and will cease to read in anymore ATM
cell data from the Receive UTOPIA Interface block; until
RxUClav toggles “high” again.
The RxFIFO accumulates enough cell data to make
up a complete ATM cell shortly before clock edge #5.
At this point the Receive UTOPIA Interface block
reflects this fact by asserting the RxUClav signal. The
ATM Layer processor detects that the RxUClav signal
has toggled “high” at clock edge #5. Consequently,
the ATM Layer processor then asserts the RxUEn
signal (e.g., toggles it “l(fā)ow”) after clock edge #5. The
Receive UTOPIA Interface block detects the fact that
the RxUEn input pin has been asserted at clock edge
#6. The Receive UTOPIA Interface block then re-
sponds to this signaling by placing the first word of
the next cell on the Receive UTOPIA Data bus. After-
wards, the ATM Layer processor continues to read in
the remaining words of this cell.
3.4.2.2.1.3Resetting the RxFIFO via Software
Command
The UNI allows for reseting the RxFIFO, via Software
Command, without the need to implement a master
reset of the entire UNI device. This can be accom-
plished by writing the appropriate data to bit 6
(RxFIFO Reset) of the Receive UTOPIA Interrupt En-
able/Status Register as depicted below.
Once the RxFIFO has been reset, then the contents of
the RxFIFO will be “flushed” and the Receive FIFO
Status register will reflect the “RxFIFO Empty” status.
3.4.2.2.1.4Monitoring the RxFIFO Status
The local
μ
P has the ability to poll and monitor the
status of the RxFIFO via the Receive UTOPIA FIFO
Status Register. The bit format of this register is
presented below.
The following tables define the values for Bits 1 and 0
and the corresponding meaning.
Receive UTOPIA—Interrupt/Status Register (Address—6Bh)
B
IT
7
B
IT
6
B
IT
5
B
IT
4
B
IT
3
B
IT
2
B
IT
1
B
IT
0
Unused
RxFIFO
Reset
RxFIFO
Overrun Inter-
rupt Enable
RxFIFO
Underrun
Interrupt
Enable
RCOCA
Interrupt
Enable
RxFIFO
Overrun Inter-
rupt Enable
RxFIFO
Underrun
Interrupt
Enable
RxFIFO
COCA
Int. Status
R/O
R/W
R/W
R/W
R/W
RUR
RUR
RUR
Receive UTOPIA FIFO Status Register (Address = 6Dh)
B
IT
7
B
IT
6
B
IT
5
B
IT
4
B
IT
3
B
IT
2
B
IT
1
B
IT
0
Unused
RxFIFO Full
RxFIFO Empty
RO
RO
RO
RO
RO
RO
RO
RO
RxFIFO Full
R
X
FIFO F
ULL
(B
IT
1)
M
EANING
0
RxFIFO is not full.
1
RxFIFO is full, and if the next operation by the ATM Layer processor is not a read operation, then the
RxFIFO could be overrun.