XRT74L73
3 CHANNEL, ATM UNI/PPP DS3/E3 FRAMING CONTROLLER
REV. P1.0.1
PRELIMINARY
243
The Receive DS3 Framer will assert the RxOOF
output pin (e.g., toggles it "High").
Bit 4 (RxOOF) within the Rx DS3 Configuration and
Status Register will be set to "1" as depicted below.
RX DS3 CONFIGURATION AND STATUS REGISTER, (ADDRESS = 0X10)
Rx DS3 Configuration and Status Register, (Address
= 0x10)
The Receive DS3 Framer block will also issue a
Change in OOF Status interrupt request, anytime
there is a change in the OOF status.
4.3.2.3
Forcing a Reframe via Software Com-
mand
The Framer IC permits the user to force a reframe
procedure of the Receive DS3 Framer block via soft-
ware command. If a "1" is written into Bit 0 of the I/O
Control Register, as depicted below, then the Receive
DS3 Framer will be forced into the Frame Acquisition
Mode, (or more specifically, in the F-Bit Search State
per Figure 88 ). Afterwards, the Receive DS3 Framer
block will begin its search for valid F-Bits. The Fram-
er IC will also respond to this command by asserting
the RxOOF output pin, and generating a Change in
OOF Status interrupt.
4.3.2.4
DS3 Framer block
The user can monitor the number of framing bit errors
(M and F bits) that have been detected by the Re-
Performance Monitoring of the Receive
ceive DS3 Framer block. This is accomplished by pe-
riodically reading the PMON Framing Bit Error Count
Registers (Address = 0x52 and 0x53), as depicted
below.
B
IT
7
B
IT
6
B
IT
5
B
IT
4
B
IT
3
B
IT
2
B
IT
1
B
IT
0
RxAIS
RxLOS
RxIdle
RxOOF
Int LOS
Disable
Framing on
Parity
F-Sync Algo
M-Sync Algo
R/O
R/O
R/O
R/O
R/W
R/W
R/W
R/W
X
X
X
X
X
X
X
X
I/O CONTROL REGISTER (ADDRESS = 0X01)
B
IT
7
B
IT
6
B
IT
5
B
IT
4
B
IT
3
B
IT
2
B
IT
1
B
IT
0
Disable
TxLOC
LOC
Disable
RxLOC
AMI/ZeroSup*
Unipolar/
Bipolar*
TxLine CLK
Invert
RxLine CLK
Invert
Reframe
R/W
RO
R/W
R/W
R/W
R/W
R/W
R/W
1
0
1
0
0
0
0
1
PMON FRAMING BIT ERROR EVENT COUNT REGISTER - MSB (ADDRESS = 0X52)
B
IT
7
B
IT
6
B
IT
5
B
IT
4
B
IT
3
B
IT
2
B
IT
1
B
IT
0
F-Bit Error Count - High Byte
RUR
RUR
RUR
RUR
RUR
RUR
RUR
RUR
1
0
1
0
0
0
0
0
PMON FRAMING BIT ERROR EVENT COUNT REGISTER - LSB (ADDRESS = 0X53)
B
IT
7
B
IT
6
B
IT
5
B
IT
4
B
IT
3
B
IT
2
B
IT
1
B
IT
0
F-Bit Error Count - Low Byte
RUR
RUR
RUR
RUR
RUR
RUR
RUR
RUR
0
0
0
0
0
0
0
0