
XRT74L73
3 CHANNEL, ATM UNI/PPP DS3/E3 FRAMING CONTROLLER
PRELIMINARY
REV. P1.0.1
248
1.
The Receive DS3 Framer block will inform the
μP/μC of this occurrence by generating a Detec-
tion of P-Bit Error interrupt,
2.
The Receive DS3 Framer block will alter the
value of the FEBE bits, (to a pattern other than
111) that the Near-End Transmit DS3 Framer will
be transmitting back to the remote Terminal.
PMON PARITY ERROR EVENT COUNT REGISTER - MSB (ADDRESS = 0X54)
3.
The XRT74L73 Framer IC will increment the
PMON Parity Error Event Count Registers
(Address = 0x54 and 0x55) for each detected
parity error, in the incoming DS3 data stream.
The bit-format of these two registers follows.
When the μP reads these registers, it will read in the
number of parity-bit errors that have been detected
by the Receive DS3 Framer block, since the last time
these registers were read. These registers are reset
upon read.
N
OTE
:
When the Framing with Parity option is selected, the
Receive DS3 Framer block will declared an OOF condition
if P-bit errors were detected in two out of 5 consecutive
DS3 M-frames.
4.3.2.6.2
CP-Bit Checking/Options
CP-bits are very similar to P-bits except for the follow-
ing.
1.
CP-bits are used to permit performance monitor-
ing over an entire DS3 path (e.g., from the source
terminal) through any number of mid-network ter-
minals to the sink terminal).
2.
P-bits are used to permit performance monitoring
of a DS3 data stream, as it is transmitted from
one terminal to an adjacent terminal.
How CP-Bits are Processed
The following section describes how the CP-bits are
processed at three locations.
The Source Terminal Equipment
The Mid-Network Terminal Equipment
The Sink Terminal Equipment
Figure_62 presents a simple illustration of the loca-
tions of these three types of Terminal Equipment,
within the Wide-Area Network.
B
IT
7
B
IT
6
B
IT
5
B
IT
4
B
IT
3
B
IT
2
B
IT
1
B
IT
0
Parity Error Count - High Byte
RO
RO
RO
RO
RO
RO
RO
RO
0
0
0
0
0
0
0
0
PMON PARITY ERROR EVENT COUNT REGISTER - LSB (ADDRESS = 0X55)
B
IT
7
B
IT
6
B
IT
5
B
IT
4
B
IT
3
B
IT
2
B
IT
1
B
IT
0
Parity Error Count - "Low" Byte
RO
RO
RO
RO
RO
RO
RO
RO
0
0
0
0
0
0
0
0