參數資料
| 型號： | XRT83L34IV |
| 廠商： | Exar Corporation |
| 文件頁數： | 10/99頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC LIU T1/E1/J1 QUAD 128TQFP |
| 標準包裝： | 72 |
| 類型： | 線路接口裝置（LIU） |
| 驅動器/接收器數： | 4/4 |
| 規(guī)程： | T1，E1，J1 |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 128-LQFP |
| 供應商設備封裝： | 128-TQFP（14x20） |
| 包裝： | 托盤 |
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XRT83L34
xr
REV. 1.0.1
QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
15
ALE_AS
TAOS_2
71
I
Address Latch Enable/Address Strobe/Transmit All Ones Input - Chan-
nel 2:
The exact function of this input pin depend upon whether the XRT83L34
device has been configured to operate in the HOST or Hardware Mode, as
described below.
HOST Mode Operation - Address Latch Enable/Address Strobe Input
Pin:
The exact function of this input pin depends upon which mode the Micropro-
cessor Interface has been configured to operate in, as described below.
Intel-Asynchronous Mode - ALE - Address Latch Enable:
If the Microprocessor Interface (of the XRT83L34 device) has been config-
ured to operate in the Intel-Asynchronous Mode, then this active-high input
pin is used to latch the address (present at the Microprocessor Interface
Address Bus pins (A[6:0]) into the XRT83L34 Microprocessor Interface bloc
and to indicate the start of a READ or WRITE cycle.
Pulling this input pin "high" enables the input bus drivers for the Address Bus
Input pins (A[6:0]). The contents of the Address Bus will be latched into the
XRT83L34 Microprocessor Interface circuitry, upon the falling edge of this
input signal.
Motorola Asynchronous Mode - AS* - Address Strobe Input:
If the Microprocessor Interface has been configured to operate in the Motor-
ola-Asynchronous Mode, then pulling this input pin "LOW enables the "input"
bus drivers for the Address Bus Input pins.
During each READ or WRITE operation, the user is expected to drive this
input pin "LOW" after (or around the time that) he/she has places the address
(of the "target" register) onto the Address Bus pins (A[6:0]). The user is then
expected to hold this input pin "LOW" for the remainder of the READ or
WRITE cycle.
NOTE: It is permissible to tie the ALE_AS* and CS* input pins together..
Read and Write operations will be performed properly if ALE_AS is
driven "LOW" coincident to whenever CS* is also driven "LOW".
Hardware Mode Operation - Transmit All “Ones” Channel_2 - Hardware
Mode
NOTE: Internally pulled “Low” with a 50k
resistor.
CS
TAOS_3
72
I
Chip Select Input/Transmit All Ones Input - Channel 3:
The exact function of this input pin depends upon whether the XRT83L34
device has been configured to operate in the HOST or Hardware Mode, as
described below.
HOST Mode Operation - Chip Select Input pin:
The user must assert this active-low signal in order to select the Micropro-
cessor Interface for READ and WRITE operations between the Microproces-
sor and the XRT83L34 on-chip registers.
Hardware Mode Operation - Transmit All Ones Input - Channel 3:
NOTE: Internally pulled “Low” with a 50k
resistor.
SIGNAL NAME
PIN #TYPE
DESCRIPTION
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相關代理商/技術參數 |
參數描述 |
|---|---|
| XRT83L34IV-F | 功能描述:網絡控制器與處理器 IC RoHS:否 制造商:Micrel 產品:Controller Area Network (CAN) 收發(fā)器數量: 數據速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| XRT83L34IVTR | 功能描述:外圍驅動器與原件 - PCI RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| XRT83L34IVTR-F | 功能描述:外圍驅動器與原件 - PCI RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| XRT83L38 | 制造商:EXAR 制造商全稱:EXAR 功能描述:OCTAL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR |
| XRT83L38_07 | 制造商:EXAR 制造商全稱:EXAR 功能描述:OCTAL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR |
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