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參數(shù)資料
| 型號： | XRT83L34IV |
| 廠商： | Exar Corporation |
| 文件頁數(shù)： | 78/99頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC LIU T1/E1/J1 QUAD 128TQFP |
| 標準包裝： | 72 |
| 類型： | 線路接口裝置（LIU） |
| 驅動器/接收器數(shù)： | 4/4 |
| 規(guī)程： | T1，E1，J1 |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 128-LQFP |
| 供應商設備封裝： | 128-TQFP（14x20） |
| 包裝： | 托盤 |
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XRT83L34
xr
REV. 1.0.1
QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
5
PIN DESCRIPTION BY FUNCTION
RECEIVE SECTIONS
SIGNAL NAME
PIN #
TYPE
DESCRIPTION
RLOS_0
RLOS_1
RLOS_2
RLOS_3
4
28
75
99
O
Receiver LOS (Loss of Signal) Defect Indicator Output for Channel _n
This output pin indicates whether or not the Receive Section associated with
Channel n (within the LIU device) is declaring the LOS defect condition, as
depicted below.
LOGIC LOW - Indicates that this particular channel is currently not declaring
the LOS defect condition.
LOGIC HIGH - Indicates that this particular channel is currently declaring the
LOS defect condition.
RCLK_0
RCLK_1
RCLK_2
RCLK_3
5
27
76
98
O
Receiver Clock Output for Channel _n
The Receive Section (of a given channel within the XRT83L34 device) will
update the RPOS_n and RNEG_n/LCV_n output pins upon either the rising
or falling edge of this output clock signal (depending upon user configura-
tion).
RNEG_0/
LCV_0
RNEG_1/
LCV_1
RNEG_2/
LCV_2
RNEG_3/
LCV_3
6
26
77
97
O
Receiver Negative-Polarity Data Output/Line Code Violation Indicator
Output - Channel n:
The exact function of this output pin depends upon whether the XRT83L34
device has been configured to operate in the Single-Rail or Dual-Rail Mode,
as described below.
Dual-Rail Mode Operation - Receive Negative-Polarity Data Output -
RNEG_n:
The Receive Section of Channel n will output the negative-polarity portion of
the recovered incoming DS1/E1 data (from the remote terminal equipment)
via this output pin. Each channel (within the XRT83L34 device) will update
this incoming DS1/E1 data upon the "user-selected" edge of the RCLK_n
output signal.
The "Positive-Polarity Portion" of the recovered incoming DS1/E1 data will
be output via the RPOS_n output pin.
Single-Rail Mode Operation - Line Code Violation Indicator Output -
LCV_n:
The Receive Section of Channel n will pulse this output pin "high" (for one
RCLK_n period) each time it detects a Line Code Violation within the incom-
ing DS1/E1 line signal. Each channel (within the XRT83L34 device) will
update this output pin upon the "user-selected" edge of the RCLK_n output
signal.
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| XRT83L34IV-F | 功能描述:網(wǎng)絡控制器與處理器 IC RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| XRT83L34IVTR | 功能描述:外圍驅動器與原件 - PCI RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| XRT83L34IVTR-F | 功能描述:外圍驅動器與原件 - PCI RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| XRT83L38 | 制造商:EXAR 制造商全稱:EXAR 功能描述:OCTAL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR |
| XRT83L38_07 | 制造商:EXAR 制造商全稱:EXAR 功能描述:OCTAL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR |
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