QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. 1.0.1 54 Asy" />
參數(shù)資料
型號(hào)： XRT83L34IV
廠商： Exar Corporation
文件頁(yè)數(shù)： 53/99頁(yè)
文件大?。?/td> 0K
描述： IC LIU T1/E1/J1 QUAD 128TQFP
標(biāo)準(zhǔn)包裝： 72
類型： 線路接口裝置（LIU）
驅(qū)動(dòng)器/接收器數(shù)： 4/4
規(guī)程： T1，E1，J1
電源電壓： 3.135 V ~ 3.465 V
安裝類型： 表面貼裝
封裝/外殼： 128-LQFP
供應(yīng)商設(shè)備封裝： 128-TQFP（14x20）
包裝： 托盤
xr
XRT83L34
QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. 1.0.1
54
Asynchronous" Mode Read Operation.
THE INTEL-ASYNCHRONOUS WRITE CYCLE
If the Microprocessor Interface (of the XRT83L34 device) has been configured to operate in the Intel-
Asynchronous Mode, then the Microprocessor should do all of the following anytime that it wishes to write a
byte of data into a register within the XRT83L34 device.
1. Place the address of the "target" register (within the XRT83L34 device) on the Address Bus Input pins,
A[6:0].
2. While the Microprocessor is placing the address value on the Address bus, the Address Decoding circuitry
(within the user’s system) should assert the CS* (Chip Select) input pin of the XRT83L34 device by tog-
gling it "LOW". This action enables further communication between the Microprocessor and the XRT83L34
Microprocessor Interface.
3. Toggle the ALE/AS (Address Latch Enable) input pin "HIGH". This step enables the "Address Bus" input
drivers, within the Microprocessor Interface block of the XRT83L34 device.
4. After allowing the data on the Address Bus pins to settle (by waiting the appropriate "Address Set-up" time)
the Microprocessor should toggle the ALE/AS input pin "LOW". This step causes the XRT83L34 device to
"latch" the contents of the "Address Bus" into its internal circuitry. At this point, the address of the register
(within the XRT83L34 device) has now been selected.
5. Next, the Microprocessor should then place the byte that it intends to write into the "target" register (within
the XRT83L34 device), on the Bi-Direction Data Bus pins (D[7:0]).
6. Afterwards, the Microprocessor should then indicate that this current bus cycle is a "Write" Operation; by
toggling the WR*/R/W (Write Strobe) input pin "LOW". This active also enables the "Bi-Directional" Data
Bus Input Drivers of the XRT83L34 device. At this point, the "Bi-Directional" data bus input drivers will pro-
ceed to drive the contents (currently residing on the Bi-Directional Data Bus into the register that corre-
sponds with the "latched" address.
7. Immediately after the Microprocessor toggles the "Write Strobe" (WR*/R/W*) signal "LOW" the XRT83L34
device will continue to drive the "RDY*/DTACK*" output pin "high". The XRT83L34 device does this in
order to inform the Microprocessor that the data (to be written into the "target" address location, within the
XRT83L34 device) is "NOT READY" to be latched into the Microprocessor Interface block circuitry (within
FIGURE 25. ILLLUSTRATION OF AN INTEL-ASYNCHRONOUS MODE READ OPERATION
ALE/AS
RD*/DS*
A[6:0]
CS*
D[7:0]
RDY/DTACK*
Not Valid
Valid Data
Address of Target Register
WR*/R/W*
Microprocessor places “target”
Address value on A[6:0]
Address Decoding
Circuitry asserts
CS*
RDY* toggles “l(fā)ow” to indicate that
Valid data can be read from D[7:0]
Read Operation begins
Here
RDY* toggle “high”
after Completion
Of Read Operation
Read Operation is
Terminated Here
Microprocessor Interface latches contents on
A[6:0] upon falling edge of ALE
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