QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. 1.0.1 22 TRA" />
參數(shù)資料
型號(hào)： XRT83L34IV
廠商： Exar Corporation
文件頁(yè)數(shù)： 18/99頁(yè)
文件大?。?/td> 0K
描述： IC LIU T1/E1/J1 QUAD 128TQFP
標(biāo)準(zhǔn)包裝： 72
類型： 線路接口裝置（LIU）
驅(qū)動(dòng)器/接收器數(shù)： 4/4
規(guī)程： T1，E1，J1
電源電壓： 3.135 V ~ 3.465 V
安裝類型： 表面貼裝
封裝/外殼： 128-LQFP
供應(yīng)商設(shè)備封裝： 128-TQFP（14x20）
包裝： 托盤
xr
XRT83L34
QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. 1.0.1
22
TRATIO
INT
119
I
O
Transmitter Transformer Ratio Select - Hardware Mode
In external termination mode (TXSEL = 0), setting this pin "High" selects a
transformer ratio of 1:2 for the transmitter. A "Low" on this pin sets the trans-
mitter transformer ratio to 1:2.45. In the internal termination mode the
transmitter transformer ratio is permanently set to 1:2 and the state of this pin
is ignored.
Interrupt Output - Host Mode
This pin is asserted “Low” to indicate an alarm condition.
NOTE: This pin is an open drain output and requires an external 10k
pull-
up resistor.
RESET
121
I
Hardware Reset (Active "Low")
When this pin is tied “Low” for more than 10s, the device is put in the reset
state.
Pulling RESET and ICT pins “Low” simultaneously will put the chip in factory
test mode. This condition should not be permitted during normal operation.
NOTE: Internally pulled “High” with a 50k
resistor.
SR/DR
16
I
Single-Rail/Dual-Rail Data Format
Connect this pin "Low" to select transmit and receive data format in Dual-rail
mode. In this mode, HDB3 or B8ZS encoder and decoder are not available.
Connect this pin "High" to select single-rail data format.
NOTE: Internally pulled "Low" with a 50k
resistor.
LOOP1_0
LOOP0_0
LOOP1_1
LOOP0_1
LOOP1_2
LOOP0_2
LOOP1_3
LOOP0_3
D[7]
D[6]
D[5]
D[4]
D[3]
D[2]
D[1]
D[0]
42
43
44
45
46
47
48
49
42
43
44
45
46
47
48
49
I/O
Loop-Back Control Pins - Hardware Mode:
Loop-back control pin 1 - Channel _0
Loop-back control pin 0 - Channel _0
Loop-back control pin 1 - Channel _1
Loop-back control pin 0 - Channel _1
Loop-back control pin 1 - Channel _2
Loop-back control pin 0 - Channel _2
Loop-back control pin 1 - Channel _3
Loop-back control pin 0 - Channel _3
Microprocessor R/W Data bits [7:0] - Host Mode
These pins are microprocessor data bus pins.
NOTE: These pins are internally pulled “Low” with a 50k
resistor.
SIGNAL NAME
PIN #TYPE
DESCRIPTION
LOOP1_n
LOOP0_n
0
1
0
1
MODE
Normal Mode No Loop-back Channel_n
Local Loop-Back Channel_n
Remote Loop-Back Channel_n
Digital Loop-Back Channel_n
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XRT83L34IVTR 功能描述:外圍驅(qū)動(dòng)器與原件 - PCI RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray
XRT83L34IVTR-F 功能描述:外圍驅(qū)動(dòng)器與原件 - PCI RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray
XRT83L38 制造商:EXAR 制造商全稱:EXAR 功能描述:OCTAL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
XRT83L38_07 制造商:EXAR 制造商全稱:EXAR 功能描述:OCTAL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
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