參數(shù)資料
型號(hào): XRT83L34IV
廠商: Exar Corporation
文件頁(yè)數(shù): 59/99頁(yè)
文件大?。?/td> 0K
描述: IC LIU T1/E1/J1 QUAD 128TQFP
標(biāo)準(zhǔn)包裝: 72
類(lèi)型: 線路接口裝置(LIU)
驅(qū)動(dòng)器/接收器數(shù): 4/4
規(guī)程: T1,E1,J1
電源電壓: 3.135 V ~ 3.465 V
安裝類(lèi)型: 表面貼裝
封裝/外殼: 128-LQFP
供應(yīng)商設(shè)備封裝: 128-TQFP(14x20)
包裝: 托盤(pán)
XRT83L34
xr
REV. 1.0.1
QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
59
8. After waiting the appropriate time for the data (on the bi-directional data bus) to settle and can be safely
accepted by the Microprocessor, the XRT83L34 device will indicate that this data can now be latched into
the "target" address location by toggling the "RDY*/DTACK*" output pin "LOW.
9. After the Microprocessor detects the RDY*/DTACK* signal (from the XRT83L34 device) toggling "LOW", it
can then terminate the WRITE cycle by toggling the "RD*/DS*" (Data Strobe) input pin "HIGH".
NOTE: Once the user toggles the "RD*/DS* (Data Strobe) input pin "HIGH", then the following two things will happen.
1. The XRT83L34 device will latch the contents of the bi-directional data bus into the Microprocessor Inter-
face block.
2. The XRT83L34 device will terminate the "WRITE" cycle.
Figure _ presents a timing diagram that illustrates the behavior of the Microprocessor Interface signals, during a "Motorola-
Asynchronous" Write Operation.
FIGURE 28. ILLUSTRATION OF A MOTOROLA-ASYNCHRONOUS WRITE OPERATION
ALE/AS*
A[6:0]
CS*
D[7:0]
RD*/DS*
RDY*/DTACK*
Data to be Written
Address of Target Register
WR/R/W*
Microprocessor places “target”
Address value on A[6:0]
Address Decoding
Circuitry asserts
CS*
Microprocessor toggles “R/W*” low
To Denote WRITE operation
Write Operation begins
Here
DTACK* toggles “l(fā)ow” to indicate
That valid data can be latched into
“target” Address location of chip
Write Operation is
Terminated Here
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