QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. 1.0.1 42 N+1" />
參數(shù)資料
型號(hào)： XRT83L34IV
廠商： Exar Corporation
文件頁數(shù)： 40/99頁
文件大?。?/td> 0K
描述： IC LIU T1/E1/J1 QUAD 128TQFP
標(biāo)準(zhǔn)包裝： 72
類型： 線路接口裝置（LIU）
驅(qū)動(dòng)器/接收器數(shù)： 4/4
規(guī)程： T1，E1，J1
電源電壓： 3.135 V ~ 3.465 V
安裝類型： 表面貼裝
封裝/外殼： 128-LQFP
供應(yīng)商設(shè)備封裝： 128-TQFP（14x20）
包裝： 托盤
xr
XRT83L34
QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. 1.0.1
42
N+1 redundancy has one backup card for N primary cards. Due to impedance mismatch and signal contention,
external relays are necessary when using this redundancy scheme. The advantage of relays is that they create
complete isolation between the primary cards and the backup card. This allows all transmitters and receivers
on the primary cards to be configured in internal impedance mode, providing one bill of materials for all
interface modes of operation. The transmit and receive sections of the XRT83L34 are described separately.
TRANSMIT
For N+1 redundancy, the transmitters on all cards should be programmed for internal impedance mode
providing one bill of materials for T1/E1/J1. The transmitters on the backup card do not have to be tri-stated. To
swap the primary card, close the desired relays, and tri-state the transmitters on the failed primary card. A
0.68
F capacitor is used in series with TTIP for blocking DC bias. See Figure 18 for a simplified block diagram
of the transmit section for an N+1 redundancy scheme.
NOTE: For simplification, the over voltage protection circuitry was omitted.
FIGURE 18. SIMPLIFIED BLOCK DIAGRAM - TRANSMIT SECTION FOR N+1 REDUNDANCY
B ackp la ne Interface
P rim ary C a rd
X R T8 3L4
Tx
Line Interface C ard
0.6 8 F
T 1/E 1 Line
P rim ary C ard
X R T 83L3 4
Tx
P rim ary C ard
X R T8 3L34
Tx
B a ckup C ard
X R T8 3L34
Tx
T 1/E 1 Line
TxTS EL =1, Internal
T xT S EL=1, Inte rnal
1:2 o r 1 :2.45
0.6 8 F
0.68 F
1:2 o r 1 :2.45
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