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參數(shù)資料
| 型號(hào)： | XRT83L34IV |
| 廠商： | Exar Corporation |
| 文件頁數(shù)： | 52/99頁 |
| 文件大小： | 0K |
| 描述： | IC LIU T1/E1/J1 QUAD 128TQFP |
| 標(biāo)準(zhǔn)包裝： | 72 |
| 類型： | 線路接口裝置（LIU） |
| 驅(qū)動(dòng)器/接收器數(shù)： | 4/4 |
| 規(guī)程： | T1，E1，J1 |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 128-LQFP |
| 供應(yīng)商設(shè)備封裝： | 128-TQFP（14x20） |
| 包裝： | 托盤 |
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XRT83L34
xr
REV. 1.0.1
QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
53
CONFIGURING THE MICROPROCESSOR INTERFACE TO OPERATE IN THE INTEL-ASYNCHRONOUS
MODE
The user can configure the Microprocessor Interface to operate in the Intel-Asynchronous Mode by tying the
UPTS1 (Pin 106) to GND.
Finally, if the Microprocessor Interface has been configured to operate in the Intel-Asynchronous Mode, then it
will perform READ and WRITE operations as described below.
THE INTEL-ASYNCHRONOUS READ CYCLE
If the Microprocessor Interface (of the XRT83L34 device) has been configured to operate in the Intel-
Asynchronous Mode, then the Microprocessor should do all of the following, anytime it wishes to read out the
contents of a register.
1. Place the address of the "target" register (within the XRT83L34 device) on the Address Bus input pins,
A[6:0].
2. While the Microprocessor is placing this address value on the Address Bus, the Address Decoding circuitry
(within the user’s system) should assert the CS* (Chip Select) input pin of the XRT83L34 device, by tog-
gling it "LOW". This action enables further communication between the Microprocessor and the XRT83L34
Microprocessor Interface block
3. Toggle the ALE/AS (Address Latch Enable) input pin "HIGH". This step enables the "Address Bus" input
drivers, within the Microprocessor Interface block of the XRT83L34 device.
4. After allowing the data on the Address Bus pins to settle (by waiting the appropriate "Address Data Setup
time"), the Microprocessor should toggle the ALE/AS input pin "LOW". This step causes the XRT83L34
device to "latch" the contents of the "Address Bus" into its internal circuitry. At this point, the address of the
register (within the XRT83L34 device) has now been selected.
5. Next, the Microprocessor should indicate that this current bus cycle is a "READ" operation by toggling the
"RD*/DS*" (Read Strobe) input pin "LOW". This action also enable the bi-directional data bus output driv-
ers of the XRT83L34 device. At this point, the "Bi-Directional" Data Bus output drivers will proceed to drive
the contents of the "latched" addressed onto the bi-directional data bus, D[7:0].
6. Immediately after the Microprocessor toggles the "Read Strobe" (RD*/DS*) signal "low", the XRT83L34
device will continue to drive the RDY*/DTACK* output pin "high". The XRT83L34 device does this in order
to inform the Microprocessor that the data (to be read from the data bus) is "NOT READY" to be "latched"
into the Microprocessor. In this case, the Microprocessor should continue to hold the "Read Strobe" (RD*/
DS*) signal "LOW" until it detects the "RDY*/DTACK*" output pin toggling "LOW".
7. After some settling time, the data on the "Bi-Directional" data bus will stabilize and can be read by the
Microprocessor. At this time, the XRT83L34 device will indicate that this data can be read by toggling the
RDY*/DTACK* (READY) signal "LOW".
8. After the Microprocessor detects the RDY*/DTACK* signal (from the XRT83L34 device) toggling "LOW", it
can then terminate the READ cycle by toggling the RD*/DS* (READ Strobe) input pin "HIGH".
Figure 25 presents a timing diagram that illustrates the behavior of the Microprocessor Interface signals, during an "Intel-
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| XRT83L34IV-F | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| XRT83L34IVTR | 功能描述:外圍驅(qū)動(dòng)器與原件 - PCI RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| XRT83L34IVTR-F | 功能描述:外圍驅(qū)動(dòng)器與原件 - PCI RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| XRT83L38 | 制造商:EXAR 制造商全稱:EXAR 功能描述:OCTAL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR |
| XRT83L38_07 | 制造商:EXAR 制造商全稱:EXAR 功能描述:OCTAL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR |
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