QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. 1.0.1 20 CLO" />
參數(shù)資料
型號: XRT83L34IV
廠商: Exar Corporation
文件頁數(shù): 16/99頁
文件大?。?/td> 0K
描述: IC LIU T1/E1/J1 QUAD 128TQFP
標準包裝: 72
類型: 線路接口裝置(LIU)
驅動器/接收器數(shù): 4/4
規(guī)程: T1,E1,J1
電源電壓: 3.135 V ~ 3.465 V
安裝類型: 表面貼裝
封裝/外殼: 128-LQFP
供應商設備封裝: 128-TQFP(14x20)
包裝: 托盤
xr
XRT83L34
QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. 1.0.1
20
CLOCK SYNTHESIZER
SIGNAL NAME
PIN #
TYPE
DESCRIPTION
MCLKE1
32
I
E1 Master Clock Input
A 2.048MHz clock for with an accuracy of better than ±50ppm and a duty
cycle of 40% to 60% can be provided at this pin.
In systems that have only one master clock source available (E1 or T1), that
clock should be connected to both MCLKE1 and MCLKT1 inputs for proper
operation.
NOTES:
1.
All channels of the XRT83L34 must be operated at the same clock
rate, either T1, E1 or J1.
2.
Internally pulled “Low” with a 50k
resistor.
CLKSEL0
CLKSEL1
CLKSEL2
37
38
39
I
Clock Select inputs for Master Clock Synthesizer - Hardware mode
CLKSEL[2:0] are input signals to a programmable frequency synthesizer that
can be used to generate a master clock from an accurate external clock
source according to the following table.
The MCLKRATE control signal is generated from the state of EQC[4:0]
inputs. See Table 4 for description of Transmit Equalizer Control bits.
Host Mode: The state of these pins are ignored and the master frequency
PLL is controlled by the corresponding interface bits. See register address
1000001.
NOTE: These pins are internally pulled "Low" with a 50k
resistor.
2048
1544
MCLKE1
(kHz)
8
16
56
8
56
64
128
256
128
2048
1544
MCLKT1
(kHz)
1544
X
1544
X
2048
1544
2048
CLKOUT
(KHz)
1544
2048
1544
2048
1544
2048
1544
2048
1544
2048
1544
2048
1544
0
1
CLKSEL0
0
1
0
1
0
1
0
CLKSEL1
1
0
1
0
1
0
CLKSEL2
0
1
0
1
0
1
0
1544
2048
X
2048
1544
0
1
0
1
MCLKRATE
1
0
1
0
1
0
1
0
1
0
1
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