參數(shù)資料
型號(hào)： XRT83VSH316IB
廠商： Exar Corporation
文件頁(yè)數(shù)： 21/98頁(yè)
文件大?。?/td> 0K
描述： IC LIU SH T1/E1/J1 16CH 316STBGA
標(biāo)準(zhǔn)包裝： 60
類型： 線路接口裝置（LIU）
驅(qū)動(dòng)器/接收器數(shù)： 16/16
規(guī)程： T1，E1，J1
電源電壓： 3.14 V ~ 3.47 V
安裝類型： 表面貼裝
封裝/外殼： 316-LBGA
供應(yīng)商設(shè)備封裝： 316-STBGA（21x21）
包裝： 托盤
XRT83VSH316
25
16-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT
REV. 1.0.1
3.6
Receive Diagnostic Pattern Detection
The receive path has the ability to detect diagnostic patterns on the line side interface from the RTip/RRing
input pins (Single Rail Mode Only). The LIU can detect an All Ones (SAIS), Loss of Signal (RLOS), PRBS/
QRSS (SPRBS), or Line Code Violations (LCV).
3.6.1
RLOS (Receiver Loss of Signal, Line Side)
The XRT83VSH316 supports both G.775 or ETSI-300-233 RLOS detection scheme.
In G.775 mode, LOS is declared when the received signal is less than 375mV for 32 consecutive pulse periods
(typical). The device clears LOS when the receive signal achieves 12.5% ones density with no more than 15
consecutive zeros in a 32 bit sliding window and the signal level exceeds 425mV (typical).
In ETSI-300-233 mode the device declares LOS when the input level drops below 375mV (typical) for more
than 2048 pulse periods (1msec).
The device exits LOS when the input signal exceeds 425mV (typical) and has transitions for more than 32
pulse periods with 12.5% ones density with no more than 15 consecutive zero’s in a 32 bit sliding window.
In T1 mode RLOS is declared when the received signal is less than 320mV for 175 consecutive pulse period
(typical). The device clears RLOS when the receive signal achieves 12.5% ones density with no more than 100
consecutive zeros in a 128 bit sliding window and the signal level exceeds 425mV (typical).
3.6.2
EXLOS (Extended Loss of Signal)
By enabling the extended loss of signal by programming the appropriate channel register, the digital LOS is
extended to count 4,096 consecutive zeros before declaring LOS in T1 and E1 mode. By default, EXLOS is
disabled and LOS operates in normal mode.
3.6.3
AIS (Alarm Indication Signal, Line Side)
The XRT83VSH316 adheres to the ITU-T G.775 specification for an all ones pattern. The alarm indication
signal is set to "1" if an all ones pattern (at least 99.9% ones density) is present for T, where T is 3ms to 75ms
in T1 mode. AIS will clear when the ones density is not met within the same time period T. In E1 mode, the
AIS is set to "1" if the incoming signal has 2 or less zeros in a 512-bit window. AIS will clear when the incoming
signal has 3 or more zeros in the 512-bit window.
3.6.4
FLSD (FIFO Limit Status Detection)
The purpose of the FIFO limit status is to indicate when the Read and Write FIFO pointers are within a pre-
determined range (over-flow or under-flow indication). The FLSD is set to "1" if the FIFO Read and Write
Pointers are within ±3-Bits.
3.6.5
LCV (Line Code Violation Detection, Line Side Only)
The LIU contains 16 independent, 16-bit LCV counters. When the counters reach full-scale, they remain
saturated at 0xFFFFh until they are reset globally or on a per channel basis. For performance monitoring, the
counters can be updated globally or on a per channel basis to place the contents of the counters into holding
registers. The LIU uses an indirect address bus to access a counter for a given channel. Once the contents of
the counters have been placed in holding registers, they can be individually read.
The LCV_OF bit supports monitoring of Line Code violations or Over Flow status of the LCV counters. By
default, the LCV_OF bit monitors the Line Code Violations and will be set to a "1" if the receiver is currently
detecting line code violations or excessive zeros for HDB3 (E1 mode) or B8ZS (T1 mode). In AMI mode, the
LCV_OF will be set to a "1" if the receiver is currently detecting bipolar violations or excessive zeros. However,
if the LIU is configured to monitor the 16-bit LCV counter, the LCV_OF will be set to a "1" if the counter
saturates.
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