參數(shù)資料
型號: XRT83VSH316IB
廠商: Exar Corporation
文件頁數(shù): 28/98頁
文件大?。?/td> 0K
描述: IC LIU SH T1/E1/J1 16CH 316STBGA
標(biāo)準(zhǔn)包裝: 60
類型: 線路接口裝置(LIU)
驅(qū)動器/接收器數(shù): 16/16
規(guī)程: T1,E1,J1
電源電壓: 3.14 V ~ 3.47 V
安裝類型: 表面貼裝
封裝/外殼: 316-LBGA
供應(yīng)商設(shè)備封裝: 316-STBGA(21x21)
包裝: 托盤
XRT83VSH316
31
16-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT
REV. 1.0.1
4.1
TCLK/TPOS/TNEG Digital Inputs
In dual rail mode, TPOS and TNEG are the digital inputs for the transmit path. In single rail mode, TNEG has
no function and can be left unconnected. The XRT83VSH316 can be programmed to sample the inputs on
either edge of TCLK. By default, data is sampled on the falling edge of TCLK. To sample data on the rising
edge of TCLK, set TCLKE to "1" in the appropriate global register. Figure 18 is a timing diagram of the transmit
input data sampled on the falling edge of TCLK. Figure 19 is a timing diagram of the transmit input data
sampled on the rising edge of TCLK. The timing specifications are shown in Table 6.
FIGURE 18. TRANSMIT DATA SAMPLED ON FALLING EDGE OF TCLK
FIGURE 19. TRANSMIT DATA SAMPLED ON RISING EDGE OF TCLK
NOTE: VDD=3.3V ±5%, VDDc=1.8V ±5%, TA=25°C, Unless Otherwise Specified
TABLE 6: TIMING SPECIFICATIONS FOR TCLK/TPOS/TNEG
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
TCLK Duty Cycle
TCDU
30
50
70
%
Transmit Data Setup Time
TSU
50
-
ns
Transmit Data Hold Time
THO
30
-
ns
TCLK Rise Time (10% to 90%)
TCLKR
--
40
ns
TCLK Fall Time (90% to 10%)
TCLKF
--
40
ns
TCLK
TPOS
or
TNEG
TCLK
R
TCLK
F
T
HO
T
SU
TCLK
TPOS
or
TNEG
TCLK
F
TCLK
R
T
HO
T
SU
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