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參數(shù)資料
型號: XRT83VSH316IB
廠商: Exar Corporation
文件頁數(shù): 56/98頁
文件大小: 0K
描述: IC LIU SH T1/E1/J1 16CH 316STBGA
標準包裝: 60
類型: 線路接口裝置(LIU)
驅動器/接收器數(shù): 16/16
規(guī)程: T1,E1,J1
電源電壓: 3.14 V ~ 3.47 V
安裝類型: 表面貼裝
封裝/外殼: 316-LBGA
供應商設備封裝: 316-STBGA(21x21)
包裝: 托盤
XRT83VSH316
3
16-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT
REV. 1.0.1
1.0
PIN DESCRIPTIONS
MICROPROCESSOR
NAME
PIN
TYPE
DESCRIPTION
CS
A19
I
Chip Select Input
Active low signal. This signal enables the microprocessor interface by pulling
chip select "Low". The microprocessor interface is disabled when the chip
select signal returns "High". This pin is used for both the Parallel or the Serial
Interface modes.
NOTE: Internally pulled "High" with a 50k
resistor.
ALE_TS
D15
I
Address Latch Enable Input (Transfer Start)
See the Microprocessor section of this datasheet for a description.
NOTE: Internally pulled "Low" with a 50k
resistor.
WR_R/W
E15
I
Write Strobe Input (Read/Write)
See the Microprocessor section of this datasheet for a description.
NOTE: Internally pulled "Low" with a 50k
resistor.
RD_WE
C18
I
Read Strobe Input (Write Enable)
See the Microprocessor section of this datasheet for a description.
NOTE: Internally pulled "Low" with a 50k
resistor.
RDY_TA
R5
O
Ready Output (Transfer Acknowledge)
See the Microprocessor section of this datasheet for a description.
INT
B19
O
Interrupt Output
Active low signal. This signal is asserted "Low" when a change in alarm status
occurs. Once the status registers have been read, the interrupt pin will return
"High". GIE (Global Interrupt Enable) must be set "High" in the appropriate
global register to enable interrupt generation.
NOTE: This pin is an open-drain output that requires an external 10K
pull-up
resistor.
PCLK
U6
I
Micro Processor Clock Input
In a synchronous microprocessor interface, PCLK is used as the internal timing
reference for programming the LIU.
NOTE: Internally pulled "Low" with a 50k
resistor.
ADDR9
ADDR8
ADDR7
ADDR6
ADDR5
ADDR4
ADDR3
ADDR2
ADDR1
ADDR0
E17
D17
Y18
W18
W17
V17
V16
U16
U15
T15
I
Address Bus Input
ADDR[9:0] are a direct address bus for permitting access to the internal regis-
ters.
NOTE: Internally pulled "Low" with a 50k
resistor.
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