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參數(shù)資料
| 型號： | XRT83VSH316IB |
| 廠商： | Exar Corporation |
| 文件頁數(shù)： | 25/98頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC LIU SH T1/E1/J1 16CH 316STBGA |
| 標(biāo)準(zhǔn)包裝： | 60 |
| 類型： | 線路接口裝置（LIU） |
| 驅(qū)動器/接收器數(shù)： | 16/16 |
| 規(guī)程： | T1，E1，J1 |
| 電源電壓： | 3.14 V ~ 3.47 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 316-LBGA |
| 供應(yīng)商設(shè)備封裝： | 316-STBGA（21x21） |
| 包裝： | 托盤 |
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XRT83VSH316
28
REV. 1.0.1
16-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT
3.9
Jitter Attenuator (If enabled in the Receive Path)
The receive jitter attenuator reduces phase and frequency jitter in the recovered clock if it is enabled. The jitter
attenuator uses a data FIFO (First In First Out) with a programmable depth of 32-bit or 64-bit. If the LIU is used
for line synchronization (loop timing systems), the JA should be enabled in the receive path. When the Read
and Write pointers of the FIFO are within 2-Bits of over-flowing or under-flowing, the bandwidth of the jitter
attenuator is widened to track the short term input jitter, thereby avoiding data corruption. When this condition
occurs, the jitter attenuator will not attenuate input jitter until the Read/Write pointer’s position is outside the 2-
Bit window.
In T1 mode, the bandwidth of the JA is always set to 3Hz.
In E1 mode, the bandwidth is
programmable to either 10Hz or 1.5Hz (1.5Hz automatically selects the 64-Bit FIFO depth). The JA has a
clock delay equal to of the FIFO bit depth.
NOTE: If the LIU is used in a multiplexer/mapper application where stuffing bits are typically removed, the jitter attenuator
can be placed in the transmit path to smooth out the gapped clock. See the Transmit Section of this datasheet.
3.10
HDB3/B8ZS Decoder
In single rail mode, RPOS can decode AMI or HDB3/B8ZS signals. For E1 mode, HDB3 is defined as any
block of 4 successive zeros replaced with 000V or B00V, so that two successive V pulses are of opposite
polarity to prevent a DC component. In T1 mode, 8 successive zeros are replaced with 000VB0VB. If the
HDB3/B8ZS decoder is selected, the receive path removes the V and B pulses so that the original data is
output to RPOS.
3.10.0.1
RPOS/RNEG/RCLK
The digital output data can be programmed to either single rail or dual rail formats. Figure 14 is a timing
diagram of a repeating "0011" pattern in single-rail mode. Figure 15 is a timing diagram of the same fixed
pattern in dual rail mode.
FIGURE 14. SINGLE RAIL MODE WITH A FIXED REPEATING "0011" PATTERN
FIGURE 15. DUAL RAIL MODE WITH A FIXED REPEATING "0011" PATTERN
RCLK
RPOS
00
0
1
RCLK
RPOS
00
0
1
RNEG
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XRT83VSH316IB-F | 功能描述:外圍驅(qū)動器與原件 - PCI 16 Channel Short-Haul RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| XRT83VSH316IB-F | 制造商:Exar Corporation 功能描述:T1/E1 LIU IC |
| XRT83VSH38 | 制造商:EXAR 制造商全稱:EXAR 功能描述:8-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT |
| XRT83VSH38ES | 功能描述:外圍驅(qū)動器與原件 - PCI 8CH T1/E1LIUSH (low cost version) RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| XRT83VSH38IB | 功能描述:接口 - 專用 8CH SH T1/E1 Line RoHS:否 制造商:Texas Instruments 產(chǎn)品類型:1080p60 Image Sensor Receiver 工作電源電壓:1.8 V 電源電流:89 mA 最大功率耗散: 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:BGA-59 |
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