
XRT83VSH316
67
16-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT
REV. 1.0.1
TABLE 31: MICROPROCESSOR REGISTER 0X005H BIT DESCRIPTION
GLOBAL REGISTER (0X005H)
BIT
NAME
FUNCTION
Register
Type
Default
Value
(HW reset)
D7
LCV_OFLW Line Code Violation / Counter Overflow Monitor Select
This bit is used to select the monitoring activity between the LCV
and the counter overflow status. When the 16-bit LCV counter sat-
urates, the counter overflow condition is activated. By default, the
LCV activity is monitored by bit D4 in register 0xN05h.
0 = Monitoring LCV
1 = Monitoring the counter overflow status
R/W
0
D6
Reserved
R/W
0
D5
Reserved
This Register Bit is Not Used
R/W
0
D4
LCVen
Line Code Violation Counter Enable
This bit is used to enable the LCV counters for all 16 channels
within the device. By default, all 16 LCV counters are disabled.
0 = Disabled
1 = LCV Counters Enabled (For all 16 Channels)
R/W
0
D3
D2
D1
D0
LCVCH3
LCVCH2
LCVCH1
LCVCH0
Line Code Violation Counter Select
These bits are used to select which channel is to be addressed for
reading the contents in register 0x0007h (LSB) and 0x0008 (MSB).
It is also used to address the counter for a given channel when
performing an update or reset on a per channel basis. By default,
Channel 0 is selected.
0000 = Channel 0
0001 = Channel 1
0010 = Channel 2
0011 = Channel 3
0100 = Channel 4
0101 = Channel 5
0110 = Channel 6
0111 = Channel 7
1000 = Channel 8
1001 = Channel 9
1010 = Channel 10
1011 = Channel 11
1100 = Channel 12
1101 = Channel 13
1110 = Channel 14
1111 = Channel 15
R/W
0