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參數(shù)資料
| 型號： | XRT83VSH316IB |
| 廠商： | Exar Corporation |
| 文件頁數(shù)： | 81/98頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC LIU SH T1/E1/J1 16CH 316STBGA |
| 標(biāo)準(zhǔn)包裝： | 60 |
| 類型： | 線路接口裝置（LIU） |
| 驅(qū)動器/接收器數(shù)： | 16/16 |
| 規(guī)程： | T1，E1，J1 |
| 電源電壓： | 3.14 V ~ 3.47 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 316-LBGA |
| 供應(yīng)商設(shè)備封裝： | 316-STBGA（21x21） |
| 包裝： | 托盤 |
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XRT83VSH316
79
16-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT
REV. 1.0.1
NOTE: The GIE bit in the global register 0x0000h must be set to "1" in addition to the individual register bits to enable the
interrupt pin.
TABLE 48: MICROPROCESSOR REGISTER 0XN05H BIT DESCRIPTION
CHANNEL N (0XN05H)
BIT
NAME
FUNCTION
Register
Type
Default
Value
(HW reset)
D7
Reserved
This Bit is Reserved
RO
0
D6
DMO
Digital Monitor Output
The digital monitor output is always active regardless if the inter-
rupt generation is disabled. This bit indicates the DMO activity. An
interrupt will not occur unless the DMOIE is set to "1" in the chan-
nel register 0xN04h and GIE is set to "1" in the global register
0x0000h.
0 = No Alarm
1 = Transmit output driver has failures
RO
0
D5
FLS
FIFO Limit Status
The FIFO limit status is always active regardless if the interrupt
generation is disabled. This bit indicates whether the RD/WR
pointers are within 3-Bits. An interrupt will not occur unless the
FLSIE is set to "1" in the channel register 0xN04h and GIE is set to
"1" in the global register 0x0000h.
0 = No Alarm
1 = RD/WR FIFO pointers are within ±3-Bits
RO
0
D4
LCV_OF
Line Code Violation / Counter Overflow
This bit serves a dual purpose. By default, this bit monitors the line
code violation activity. However, if bit 7 in register 0x0005h is set
to a "1", this bit monitors the overflow status of the internal LCV
counter. An interrupt will not occur unless the LCV_OFIE is set to
"1" in the channel register 0xN04h and GIE is set to "1" in the glo-
bal register 0x0000h.
0 = No Alarm
1 = A line code violation, bipolar violation, or excessive zeros has
occurred
RO
0
D3
Reserved
This Bit is Reserved
RO
0
D2
AISD
Alarm Indication Signal Detection
The alarm indication signal detection is always active regardless if
the interrupt generation is disabled. This bit indicates the AIS
activity. An interrupt will not occur unless the AISIE is set to "1" in
the channel register 0xN04h and GIE is set to "1" in the global reg-
ister 0x0000h.
0 = No Alarm
1 = An all ones signal is detected
RO
0
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| XRT83VSH316IB-F | 功能描述:外圍驅(qū)動器與原件 - PCI 16 Channel Short-Haul RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| XRT83VSH316IB-F | 制造商:Exar Corporation 功能描述:T1/E1 LIU IC |
| XRT83VSH38 | 制造商:EXAR 制造商全稱:EXAR 功能描述:8-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT |
| XRT83VSH38ES | 功能描述:外圍驅(qū)動器與原件 - PCI 8CH T1/E1LIUSH (low cost version) RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| XRT83VSH38IB | 功能描述:接口 - 專用 8CH SH T1/E1 Line RoHS:否 制造商:Texas Instruments 產(chǎn)品類型:1080p60 Image Sensor Receiver 工作電源電壓:1.8 V 電源電流:89 mA 最大功率耗散: 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:BGA-59 |
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