FIGURE
參數(shù)資料
型號： XRT83VSH316IB
廠商： Exar Corporation
文件頁數(shù)： 23/98頁
文件大?。?/td> 0K
描述： IC LIU SH T1/E1/J1 16CH 316STBGA
標(biāo)準(zhǔn)包裝： 60
類型： 線路接口裝置（LIU）
驅(qū)動器/接收器數(shù)： 16/16
規(guī)程： T1，E1，J1
電源電壓： 3.14 V ~ 3.47 V
安裝類型： 表面貼裝
封裝/外殼： 316-LBGA
供應(yīng)商設(shè)備封裝： 316-STBGA（21x21）
包裝： 托盤
XRT83VSH316
I
REV. 1.0.1
16-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT
TABLE OF CONTENTS
FIGURE 1. BLOCK DIAGRAM OF THE XRT83VSH316 ........................................................................................................................ 1
1.0 PIN DESCRIPTIONS .............................................................................................................................. 3
2.0 CLOCK SYNTHESIZER ....................................................................................................................... 18
FIGURE 2. SIMPLIFIED BLOCK DIAGRAM OF THE CLOCK SYNTHESIZER ............................................................................................ 18
2.1 19.44MHZ OUTPUT CLOCK REFERENCE FOR RECOVERED CLOCK SYNCHRONIZATION ................. 19
FIGURE 3. 19.44MHZ OUTPUT CLOCK REFERENCE ........................................................................................................................ 19
3.0 RECEIVE PATH LINE INTERFACE .................................................................................................... 20
FIGURE 4. SIMPLIFIED BLOCK DIAGRAM OF THE RECEIVE PATH...................................................................................................... 20
3.1 LINE TERMINATION (RTIP/RRING) .............................................................................................................. 20
3.1.1 INTERNAL TERMINATION......................................................................................................................................... 20
FIGURE 5. TYPICAL CONNECTION DIAGRAM USING INTERNAL TERMINATION .................................................................................... 21
3.2
CLOCK AND DATA RECOVERY .................................................................................................................. 22
FIGURE 6. RECEIVE DATA UPDATED ON THE RISING EDGE OF RCLK .............................................................................................. 22
FIGURE 7. RECEIVE DATA UPDATED ON THE FALLING EDGE OF RCLK ............................................................................................ 22
3.3 RECEIVE SENSITIVITY .................................................................................................................................. 23
FIGURE 8. TEST CONFIGURATION FOR MEASURING RECEIVE SENSITIVITY........................................................................................ 23
3.4 INTERFERENCE MARGIN ............................................................................................................................. 23
FIGURE 9. TEST CONFIGURATION FOR MEASURING INTERFERENCE MARGIN .................................................................................... 23
3.5 GENERAL ALARM DETECTION AND INTERRUPT GENERATION ............................................................ 24
FIGURE 10. INTERRUPT GENERATION PROCESS BLOCK .................................................................................................................. 24
3.6 RECEIVE DIAGNOSTIC PATTERN DETECTION ......................................................................................... 25
3.6.1 RLOS (RECEIVER LOSS OF SIGNAL, LINE SIDE) .................................................................................................. 25
3.6.2 EXLOS (EXTENDED LOSS OF SIGNAL) .................................................................................................................. 25
3.6.3 AIS (ALARM INDICATION SIGNAL, LINE SIDE) ...................................................................................................... 25
3.6.4 FLSD (FIFO LIMIT STATUS DETECTION) ................................................................................................................ 25
3.6.5 LCV (LINE CODE VIOLATION DETECTION, LINE SIDE ONLY).............................................................................. 25
3.7 RECEIVE DIAGNOSTIC PATTERN GENERATION ...................................................................................... 26
3.7.1 SYSTEM SIDE AIS (SAIS) .......................................................................................................................................... 26
FIGURE 11. SYSTEM SIDE SAIS RECEIVE OUTPUT ......................................................................................................................... 26
3.7.2 ATAOS (SYSTEM AUTOMATIC TRANSMIT ALL ONES)......................................................................................... 26
FIGURE 12. SIMPLIFIED BLOCK DIAGRAM OF THE ATAOS FUNCTION............................................................................................... 26
3.7.3 SYSTEM SIDE LOS (SLOS) ....................................................................................................................................... 27
FIGURE 13. SYSTEM SIDE SLOS RECEIVE OUTPUT........................................................................................................................ 27
3.8 SYSTEM SIDE SPRBS RECEIVE OUTPUT .................................................................................................. 27
3.9 JITTER ATTENUATOR (IF ENABLED IN THE RECEIVE PATH) ................................................................. 28
3.10 HDB3/B8ZS DECODER ................................................................................................................................ 28
FIGURE 14. SINGLE RAIL MODE WITH A FIXED REPEATING "0011" PATTERN................................................................................... 28
FIGURE 15. DUAL RAIL MODE WITH A FIXED REPEATING "0011" PATTERN...................................................................................... 28
3.11 RXMUTE (RECEIVER LOS WITH DATA MUTING, LINE SIDE ONLY) ...................................................... 29
FIGURE 16. SIMPLIFIED BLOCK DIAGRAM OF THE RXMUTE FUNCTION ............................................................................................ 29
4.0 TRANSMIT PATH LINE INTERFACE ................................................................................................. 30
FIGURE 17. SIMPLIFIED BLOCK DIAGRAM OF THE TRANSMIT PATH................................................................................................... 30
4.1 TCLK/TPOS/TNEG DIGITAL INPUTS ............................................................................................................ 31
FIGURE 18. TRANSMIT DATA SAMPLED ON FALLING EDGE OF TCLK ............................................................................................... 31
FIGURE 19. TRANSMIT DATA SAMPLED ON RISING EDGE OF TCLK ................................................................................................. 31
4.2 HDB3/B8ZS ENCODER .................................................................................................................................. 32
4.3 JITTER ATTENUATOR (IF ENABLED IN THE TRANSMIT PATH) .............................................................. 32
4.4 TRANSMIT DIAGNOSTIC PATTERN GENERATION ................................................................................... 33
4.4.1 LINE SIDE AIS (TRANSMIT ALL ONES) ................................................................................................................... 33
FIGURE 20. TAOS (TRANSMIT ALL ONES)...................................................................................................................................... 33
4.4.2 ATAOS (AUTOMATIC TRANSMIT ALL ONES)......................................................................................................... 33
FIGURE 21. SIMPLIFIED BLOCK DIAGRAM OF THE ATAOS FUNCTION............................................................................................... 33
4.4.3 LINE SIDE PRBS/QRSS (PSEUDO/QUASI RANDOM BIT SEQUENCE) ................................................................. 33
4.5 TRANSMIT DIAGNOSTIC PATTERN DETECTION ....................................................................................... 34
4.5.1 SLOS (SYSTEM LOSS OF SIGNAL).......................................................................................................................... 34
4.5.2 SYS_EXLOS (SYSTEM EXTENDED LOSS OF SIGNAL) ......................................................................................... 34
4.5.3 SAIS (SYSTEM ALARM INDICATION SIGNAL)........................................................................................................ 34
4.6 TRANSMIT PULSE SHAPER AND FILTER ................................................................................................... 35
4.6.1 T1 SHORT HAUL LINE BUILD OUT (LBO) ............................................................................................................... 35
4.6.2 ARBITRARY PULSE GENERATOR FOR T1 AND E1............................................................................................... 35
FIGURE 22. ARBITRARY PULSE SEGMENT ASSIGNMENT .................................................................................................................. 35
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