參數(shù)資料
型號(hào): XRT83VSH316IB
廠商: Exar Corporation
文件頁(yè)數(shù): 88/98頁(yè)
文件大?。?/td> 0K
描述: IC LIU SH T1/E1/J1 16CH 316STBGA
標(biāo)準(zhǔn)包裝: 60
類(lèi)型: 線路接口裝置(LIU)
驅(qū)動(dòng)器/接收器數(shù): 16/16
規(guī)程: T1,E1,J1
電源電壓: 3.14 V ~ 3.47 V
安裝類(lèi)型: 表面貼裝
封裝/外殼: 316-LBGA
供應(yīng)商設(shè)備封裝: 316-STBGA(21x21)
包裝: 托盤(pán)
XRT83VSH316
86
REV. 1.0.1
16-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT
D1
SRLOS
System Side Receiver Loss of Signal
The transmitter loss of signal detection is always active regardless
if the interrupt generation is disabled. This bit indicates the SRLOS
activity. An interrupt will not occur unless the SRLOSIE is set to "1"
in the channel register 0xN10h and GIE is set to "1" in the global
register 0x0000h.
0 = No Alarm
1 = AN SRLOS condition is present
RO
0
D0
SQRPD
System Side Quasi Random Pattern Detection
The quasi random pattern detection is always active regardless if
the interrupt generation is disabled. This bit indicates that a
SQRPD has been detected. An interrupt will not occur unless the
SQRPDIE is set to "1" in the channel register 0xN10h and GIE is
set to "1" in the global register 0x0000h.
0 = No Alarm
1 = A SQRP is detected
RO
0
TABLE 61: SYSTEM SIDE INTERRUPT STATUS REGISTER (0XN12H)
SYSTEM SIDE INTERRUPT STATUS REGISTER (0XN12H)
BIT
NAME
FUNCTION
Register
Type
Default
Value
(HW reset)
D[7:3]
Reserved
These Bits are Reserved
D2
SAISDIS
System Side Alarm Indication Signal Detection Interrupt Sta-
tus
0 = No change
1 = Change in status occurred
RUR
0
D1
SRLOSIS
System Side Receiver Loss of Signal Interrupt Status
0 = No change
1 = Change in status occurred
RUR
0
D0
SQRPDIS
System Side Quasi Random Pattern Detection Interrupt Status
0 = No change
1 = Change in status occurred
RUR
0
TABLE 60: SYSTEM SIDE INTERRUPT DETECTION REGISTER (0XN11H)
SYSTEM SIDE INTERRUPT DETECTION REGISTER (0XN11H)
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