XRT83VSH316
64
REV. 1.0.1
16-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT
7.4
Global Control Registers
TABLE 26: MICROPROCESSOR REGISTER 0X000H BIT DESCRIPTION
GLOBAL REGISTER (0X000H)
BIT
NAME
FUNCTION
Register
Type
Default
Value
(HW reset)
D7
SR/DR
Single Rail/Dual Rail Mode
This bit sets the LIU to receive and transmit digital data in a single
rail or a dual rail format.
0 = Dual Rail Mode
1 = Single Rail Mode
NOTE: Any time the LIU is used to generate diagnostic patterns,
the part is automatically placed in SR mode. In addition, to
detect diagnostic patterns, the LIU must be placed in SR
mode by setting this bit to "1". This applies to both the Line
Side and System Side.
R/W
0
D6
ATAOS
Line Automatic Transmit All Ones
If ATAOS is selected, an all ones pattern will be transmitted on
TTIP/TRING for any channel that experiences an RLOS condition.
If an RLOS condition does not occur, TAOS will remain inactive.
0 = Disabled
1 = Enabled
R/W
0
D5
RCLKE
Receive Clock Data
0 = RPOS/RNEG data is updated on the rising edge of RCLK
1 = RPOS/RNEG data is updated on the falling edge of RCLK
R/W
0
D4
TCLKE
Transmit Clock Data
0 = TPOS/TNEG data is sampled on the falling edge of TCLK
1 = TPOS/TNEG data is sampled on the rising edge of TCLK
R/W
0
D3
DATAP
Data Polarity
0 = Transmit input and receive output data is active "High"
1 = Transmit input and receive output data is active "Low"
R/W
0
D2
Reserved
This Register Bit is Not Used
R/W
0
D1
GIE
Global Interrupt Enable
The global interrupt enable is used to enable/disable all interrupt
activity for all 16 channels. This bit must be set "High" for the inter-
rupt pin to operate.
0 = Disable all interrupt generation
1 = Enable interrupt generation to the individual channel registers
R/W
0
D0
SRESET
Software Reset
Writing a "1" to this bit for more than 10S initiates a device reset
for all internal circuits except the microprocessor register bits. To
reset the registers to their default setting, use the Hardware Reset
pin (See the pin description for more details).
R/W
0