XRT83VSH316
70
REV. 1.0.1
16-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT
TABLE 35: MICROPROCESSOR REGISTER 0X009H BIT DESCRIPTION
GLOBAL REGISTER (0X009H)
BIT
NAME
FUNCTION
Register
Type
Default
Value
(HW reset)
D7 - D5
Reserved
These Register Bits are Not Used
R/W
0
D4
TCLKCNL
Transmit Clock Control
When this bit is pulled "High" and there is no TCLK signal present
on the transmit input path, TTIP/TRING will Transmit All "Ones"
(TAOS). By default, TTIP/TRING will Transmit All Zeros.
0 = All Zeros
1 = All Ones
R/W
0
D3
D2
D1
D0
CLKSEL3
CLKSEL2
CLKSEL1
CLKSEL0
Clock Input Select
CLKSEL[3:0] is used to select the input clock source used as the
internal timing reference.
0000 = 2.048 MHz
0001 = 1.544 MHz
1000 = 4.096 Mhz
1001 = 3.088 Mhz
1010 = 8.192 Mhz
1011 = 6.176 Mhz
1100 = 16.384 Mhz
1101 = 12.352 Mhz
1110 = 2.048 Mhz
1111 = 1.544 Mhz
R/W
0
TABLE 36: MICROPROCESSOR REGISTER 0X00AH BIT DESCRIPTION
GLOBAL REGISTER (0X00AH)
BIT
NAME
FUNCTION
Register
Type
Default
Value
(HW reset)
D7
GCHIS7
Global Channel Interrupt Status for Channel 7
0 = No interrupt activity from channel 7
1 = Interrupt was generated from channel 7
RUR
0
D6
GCHIS6
Global Channel Interrupt Status for Channel 6
0 = No interrupt activity from channel 6
1 = Interrupt was generated from channel 6
RUR
0
D5
GCHIS5
Global Channel Interrupt Status for Channel 5
0 = No interrupt activity from channel 5
1 = Interrupt was generated from channel 5
RUR
0
D4
GCHIS4
Global Channel Interrupt Status for Channel 4
0 = No interrupt activity from channel 4
1 = Interrupt was generated from channel 4
RUR
0