XRT83VSH316
68
REV. 1.0.1
16-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT
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TABLE 32: MICROPROCESSOR REGISTER 0X006H BIT DESCRIPTION
GLOBAL REGISTER (0X006H)
BIT
NAME
FUNCTION
Register
Type
Default
Value
(HW reset)
D[7:5]
Reserved
These Register Bits are Not Used
R/W
0
D4
allRST
LCV Counter Reset for All Channels
This bit is used to reset all internal LCV counters to their default
state 0x0000h. This bit must be set to "1" for 1
S.
0 = Normal Operation
1 = Resets all Counters
R/W
0
D3
allUPDATE LCV Counter Update for All Channels
This bit is used to latch the contents of all 16 counters into holding
registers so that the value of each counter can be read. The chan-
nel is addressed by using bits D[3:0] in register 0x0005h.
0 = Normal Operation
1 = Updates all Counters
R/W
0
D2
Reserved
This bit is not used
R/W
0
D1
chUPDATE LCV Counter Update Per Channel
This bit is used to latch the contents of the counter for a given
channel into a holding register so that the value of the counter can
be read. The channel is addressed by using bits D[3:0] in register
0x0005h.
0 = Normal Operation
1 = Updates the Selected Channel
R/W
0
D0
ChRST
LCV Counter Reset Per Channel
This bit is used to reset the LCV counter of a given channel to its
default state 0x0000h. The channel is addressed by using bits
D[3:0] in register 0x0005h. This bit must be set to "1" for 1
S.
0 = Normal Operation
1 = Resets the Selected Channel
R/W
0
TABLE 33: MICROPROCESSOR REGISTER 0X007H BIT DESCRIPTIO
GLOBAL REGISTER (0X007H)
BIT
NAME
FUNCTION
Register
Type
Default
Value
(HW reset)
D7
D6
D5
D4
D3
D2
D1
D0
LCVCNT7
LCVCNT6
LCVCNT5
LCVCNT4
LCVCNT3
LCVCNT2
LCVCNT1
LCVCNT0
Line Code Violation Byte Contents[7:0]
These bits contain the LSB (bits [7:0]) of the LCV counter contents
for a selected channel. The channel is addressed by using bits
D[3:0] in register 0x0005h.
RO
0