參數(shù)資料
型號(hào)： ZL50030GAC
廠商： ZARLINK SEMICONDUCTOR INC
元件分類： 路由/交換
英文描述： Flexible 4 K x 2 K Channel Digital Switch with H.110 Interface and 1 K x 1 K Local Switch
中文描述： TELECOM, DIGITAL TIME SWITCH, PBGA220
封裝： 17 X 17 MM, 1.61 MM HEIGHT, PLASTIC, MS-034, BGA-220
文件頁(yè)數(shù)： 19/73頁(yè)
文件大?。?/td> 681K
代理商： ZL50030GAC
ZL50030
Data Sheet
19
Zarlink Semiconductor Inc.
If A13 is high, the remaining address input lines are used to select the data and connection memory positions
corresponding to the serial input or output data streams as shown in Table 7 on page 20.
The Control register (CR), the Device Mode Selection register (DMS) and the Block Programming Mode register
(BPM) control all the major functions of the device. The DMS and BPM should be programmed immediately after
system power up to establish the desired switching configuration. The Control register is used to select Data or
Connection Memory for microport operations, ST-BUS output frame and clock modes, and to set Memory Block
Programing and Bit Error Rate Testing.
The Control register (CR) consists of the memory block programming bit (MBP) and the memory select bits
(MS2-0). The memory block programming bit allows users to program the entire connection memory in two frames
(see Section 8.0, “Memory Block Programming“ on page 16). The memory select bits control the selection of the
connection memories or the data memories. See Table 8 on page 35 for contents of the Control register.
The DMS register consists of the backplane and the local mode selection bits (BMS, LG31 - LG30, LG21 - LG20,
LG11 - LG10 and LG01 - LG00) that are used to enable various switching modes for the backplane and the local
interfaces respectively. See Table 9 on page 36 for the content of the DMS register.
The BPM register consists of the block programming data bits (LBPD2-0 and BBPD2-0) and the block programming
enable bit (BPE). The block programming enable bit allows users to program the entire backplane and local
connection memories in two frames (see Section 8.0, “Memory Block Programming“ on page 16). If the ODE pin is
low, the backplane CT-Bus is in input mode and the local output drivers are in high impedance state. If the ODE pin
is high, all the backplane CT-Bus and local ST-BUS I/O drivers are controlled on a per-channel basis by backplane
and local connection memories, respectively. By programming BTM2-0 bits to “110” in the backplane connection
memory, the user can control the per-channel input (can be used for high impedance) on the backplane interface.
For the local interface, users can program LTM2 -0 bits to “110” in the local connection memory to control the
per-channel input (can be used for high impedance). See Table 10 on page 37 for the content of the BPM register.
0027
H
0028
H
Local BER Input Selection Register, LBIS
Local BER Register, LBERR
0029
H
Backplane BER Input Selection Register, BBIS
002A
H
002B
H
002C
H
Backplane BER Register, BBERR
DPLL Operation Mode Register 1, DOM1
DPLL Operation Mode Register 2, DOM2
002D
H
002E
H
DPLL Output Adjustment Register, DPOA
DPLL House Keeping Register, DHKR
A13 - A0
Location
Table 6 - Address Map For Internal Registers (A13 = 0) (continued)
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