參數(shù)資料
型號： ZL50030GAC
廠商： ZARLINK SEMICONDUCTOR INC
元件分類： 路由/交換
英文描述： Flexible 4 K x 2 K Channel Digital Switch with H.110 Interface and 1 K x 1 K Local Switch
中文描述： TELECOM, DIGITAL TIME SWITCH, PBGA220
封裝： 17 X 17 MM, 1.61 MM HEIGHT, PLASTIC, MS-034, BGA-220
文件頁數(shù)： 39/73頁
文件大小： 681K
代理商： ZL50030GAC
ZL50030
Data Sheet
39
Zarlink Semiconductor Inc.
Name
Description
LIDn4-0
(See Note 1)
Local Input Delay Bits 4 - 0:
These five bits define how long the serial interface receiver
takes to recognize and to store bit 0 from the LSTio input pins: e.g., to start a new frame.
The input delay can be selected to +7 3/4 data rate clock periods from the frame
boundary.
Note 1: n denotes an LSTio stream number from 0 to 15.
Table 11 - Local Input Bit Delay Registers (LIDR0 to LIDR5) Bits
Local Input Bit Delay
Corresponding Delay Bits
LIDn4
LIDn3
LIDn2
LIDn1
LIDn0
No clock period shift (Default)
0
0
0
0
0
+
1/4
data rate clock period
0
0
0
0
1
+
1/2
data rate clock period
0
0
0
1
0
+
3/4
data rate clock period
0
0
0
1
1
+ 1 data rate clock period
0
0
1
0
0
+ 1
1/4
data rate clock period
0
0
1
0
1
+ 1
1/2
data rate clock period
0
0
1
1
0
+ 1
3/4
data rate clock period
0
0
1
1
1
+ 2 data rate clock period
0
1
0
0
0
..........
...........
+ 7
3/4
data rate clock period
1
1
1
1
1
Table 12 - Local Input Bit Delay Programming
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相關代理商/技術參數(shù)
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ZL50030GAG2 制造商:Microsemi Corporation 功能描述:SWIT FABRIC 4K X 2K/1K X 1K 3.3V/5V 220BGA - Trays 制造商:Microsemi Corporation 功能描述:PB FREE FLEX 4KX2K DX+H.110 I/FACE+1K SW 制造商:Zarlink Semiconductor Inc 功能描述:SWIT FABRIC 4K X 2K/1K X 1K 3.3V/5V 220BGA - Trays 制造商:Zarlink Semiconductor Inc 功能描述:PB FREE FLEX 4KX2K DX+H.110 I/FACE+1K SW
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