參數(shù)資料
型號(hào): ZL50030GAC
廠商: ZARLINK SEMICONDUCTOR INC
元件分類: 路由/交換
英文描述: Flexible 4 K x 2 K Channel Digital Switch with H.110 Interface and 1 K x 1 K Local Switch
中文描述: TELECOM, DIGITAL TIME SWITCH, PBGA220
封裝: 17 X 17 MM, 1.61 MM HEIGHT, PLASTIC, MS-034, BGA-220
文件頁數(shù): 64/73頁
文件大小: 681K
代理商: ZL50030GAC
ZL50030
Data Sheet
64
Zarlink Semiconductor Inc.
Figure 28 - Local Clock Timing Diagram when ST_CKo frequency = 16.384 MHz
Characteristics are over recommended operating conditions unless otherwise stated.
Typical figures are at 25
°
C and are for design aid only: not guaranteed and not subject to production testing.
Figure 29 - C1M5o Output Clock Timing Diagram
Characteristics are over recommended operating conditions unless otherwise stated.
Typical figures are at 25
°
C and are for design aid only: not guaranteed and not subject to production testing.
AC Electrical Characteristics- C1M5o Output Clock Timing
Characteristic
Sym.
Min.
Typ.
Max.
Units
Notes
1
C1M5o Period
t
C1M5oP
t
C1M5oH
t
C1M5oL
t
rC1M5o
t
fC1M5o
640.5
648
655.5
ns
C
L
= 30 pF
2
C1M5o High Time
320.2
324
327.8
ns
3
C1M5o Low Time
320.2
324
327.8
ns
4
C1M5o Rise Time
10
ns
5
C1M5o Fall Time
11
ns
AC Electrical Characteristics
- Output Clock Jitter Generation (Unfiltered)
Characteristic
Typ.
Max.
Units
Notes
1
Jitter at C1M5o (1.544MHz)
7.4
8.0
ns-pp
Device locks to 1.544 MHZ
reference input, and no jitter
present on the reference.
2
Jitter at ST_CKo0-1 (4.096MHz)
7.1
8.8
ns-pp
3
Jitter at ST_CKo0-1 (8.192MHz)
7.0
8.3
ns-pp
4
Jitter at ST_CKo0-1 (16.384MHz)
7.6
9.9
ns-pp
t
LFBOS
Backplane Frame Boundary
t
FODR16
t
FODF16
t
CL16
t
CH16
t
FPW16
t
CP16
t
rC16o
t
fC16o
ST_FPo0/1
ST_CKo0/1
(16.384 MHz)
Local Output Frame Boundary
C1M5o
(1.544 MHz)
t
fC1M5o
t
rC1M5o
t
C1M5
o
L
t
C1M5
o
P
t
C1M5
o
H
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