參數(shù)資料
型號(hào)： ZL50030GAC
廠商： ZARLINK SEMICONDUCTOR INC
元件分類： 路由/交換
英文描述： Flexible 4 K x 2 K Channel Digital Switch with H.110 Interface and 1 K x 1 K Local Switch
中文描述： TELECOM, DIGITAL TIME SWITCH, PBGA220
封裝： 17 X 17 MM, 1.61 MM HEIGHT, PLASTIC, MS-034, BGA-220
文件頁(yè)數(shù)： 24/73頁(yè)
文件大?。?/td> 681K
代理商： ZL50030GAC
ZL50030
Data Sheet
24
Zarlink Semiconductor Inc.
16.1 Reference Select and Frequency Mode MUX Circuits
The DPLL accepts two simultaneous reference input signals and operates on their rising edges. Either the primary
reference (PRI_REF) signal or the secondary reference (SEC_REF) signal can be selected to be the reference
signal (REF) to the PLL circuit. The appropriate frequency mode input (either FREQ_MOD_PRI or
FREQ_MOD_SEC) is selected to be the input of the PLL circuit. The selection is done by the State Machine Circuit
based on the current state.
The FREQ_MOD_PRI and the FREQ_MOD_SEC are 2-bit wide inputs which reflect the value in the FP1-0 and
FS1-0 bits of the DOM1 register. The primary and the secondary references operate independently from each other
and can have different frequencies. Switching the reference from one frequency to another does not require the
device reset to be applied. Table 19 on page 44 shows input frequency selection for the primary and secondary
reference respectively.
16.2 PRI and SEC MUX Circuits
The DPLL has four different modes to handle reference failure. These modes are selected by the FDM0 and FDM1
bits of the DOM2 Register. If FDM1-0 is ’10’ then the Primary reference is always used regardless of failures. If
FDM1-0 is ’11’ then the Secondary reference is always used regardless of failures. Otherwise the DPLL operates in
one of two failure detection modes: Autodetect or Manual detection mode. When the FDM0 and FDM1 bits are set
to low in the DOM2 register (‘00’), the DPLL is in the Autodetect Mode. In this mode, the outputs from the
Reference Monitor Circuits LOS_PRI and LOS_SEC are used by the State Machine Circuit. When the FDM0 bit is
set to high and FDM1 bit is set to low (‘01’), the DPLL is in the Manual Detection Mode and the LOS_PRI and
LOS_SEC signals are selected from the PRI_LOS and SEC_LOS input pins to be used by the State Machine
Circuit. See Table 20 on page 47 for selection of the Failure Detection Modes.
16.3 Frame Select MUX
When the “A Clocks” or the “B Clocks” are selected as the input reference, an 8.192 MHz clock (either C8_A_io or
C8_B_io) is provided to be the input reference to the PLL circuit. Because the output frame pulse (CT_FRAME)
must be aligned with the selected input frame pulse, the appropriate frame pulse (either FRAME_A_io or
FRAME_B_io) is selected in the Frame Select MUX circuit to be the input of the PLL circuit.
16.4 CT Clock and Frame Monitor Circuits
The CT Clock and Frame Monitor circuits check the period of the C8_A_io and the C8_B_io clocks and the
FRAME_A_io and FRAME_B_io frame pulses. According to the H.110 specification, the C8 period is 122 ns with a
tolerance of +/-35 ns measured between rising edges. If C8 falls outside the range of [87 ns, 157 ns], the clock is
rejected and the fail signal (FAIL_A or FAIL_B) becomes high. The Frame pulse period is measured with respect to
the C8 clock. The frame pulse period must have exactly 1024 C8 cycles. Otherwise, the fail signal (FAIL_A or
FAIL_B) becomes high. When the CT BUS clock and frame pulse signals return to normal, the FAIL_A or FAIL_B
signal returns to logic low.
16.5 Reference Monitor Circuits
There are two Reference Monitor Circuits: one for the primary reference (PRI_REF) and one for the secondary
reference (SEC_REF). These two circuits monitor the selected input reference signals and detect failures by setting
up the appropriate fail outputs (FAIL_PRI and FAIL_SEC). These fail signals are used in the Autodetect mode as
the LOS_PRI and LOS_SEC signals to indicate when the reference has failed. The method of generating a failure
depends on the selected reference.
When the selected reference frequency is 8.192 MHz (“A Clocks” or “B Clocks”), the fail signals are passed through
from the CT Clock and Frame Monitor circuit outputs FAIL_A and FAIL_B, and used directly as FAIL_PRI and
FAIL_SEC, accordingly.
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