參數(shù)資料
型號: ZL50030GAC
廠商: ZARLINK SEMICONDUCTOR INC
元件分類: 路由/交換
英文描述: Flexible 4 K x 2 K Channel Digital Switch with H.110 Interface and 1 K x 1 K Local Switch
中文描述: TELECOM, DIGITAL TIME SWITCH, PBGA220
封裝: 17 X 17 MM, 1.61 MM HEIGHT, PLASTIC, MS-034, BGA-220
文件頁數(shù): 23/73頁
文件大?。?/td> 681K
代理商: ZL50030GAC
ZL50030
Data Sheet
23
Zarlink Semiconductor Inc.
15.1.3 Slave Mode
In the Slave Mode, the ZL50030 is phase locked to the “A Clocks”. If the “A Clocks” become unreliable, the device
goes to stable Holdover Mode until it makes a Stratum 4 Enhanced compatible switch to the “B Clocks”. The
ZL50030 will perform all required functionality as long as the “A Clocks” and the “B Clocks” conform to the Telcordia
GR-1244-CORE jitter specifications.
In addition, the device can be used to generate a NREFo reference from its network references, LREF0-3. In most
systems NREFo is connected to either CT_REF1 or CT_REF2.
While the device is in Slave Mode and the “A Clocks” or the “B Clocks” do not recover, the designated slave can be
promoted to secondary master by system software. In that case, the network reference can be used as the
secondary reference.
Table 21 on page 49 shows how to program the DOM1 and DOM2 registers to enable the Slave Mode of the
ZL50030.
16.0 DPLL Functional Description
Figure 6 - DPLL Functional Block Diagram
PLL
(Fig 8)
PRI_REF
SEC_REF
CT Clock
and Frame
Monitor
C8_A_i
FAIL_A
State
Machine
(Fig 6)
REF_SEL
PRI_LOS Pin
SEC_LOS Pin
MTIE_RESET
(MRST bit in DOM2)
PHASE_OFFSET
(POS0-6 bits in DPOA)
SKEW_CONTROL
(SK0-2 bits in DPOA)
C32/64
CT_C8
(
C8_A_o
)
or
(
C8_B_o
)
CT_FRAME
(
FRAME_A_o
)
or
(
FRAME_B_o
)
C1M5o
HOLDOVER_RESET
(HRST bit in DOM2)
Reference
Select
MUX
Reference
Monitor
Reference
Monitor
P
S
CT Clock
and Frame
Monitor
C8_B_i
FAIL_B
AUTODETECT
(Selected by FDM0-1 bits in DOM2)
M
FREQ_MOD_PRI
(FP1-0 bits in DOM1)
FREQ_MOD_SEC
(FS1-0 bits in DOM1)
Frequency
Mode
MUX
M
HOLDOVER
MTIE_START
FREQ_MOD
REF_SELECT
LOS_PRI
LOS_SEC
FAIL_SEC
FAIL_PRI
REF
(RPS bit in DOM1)
(Selected by SP3-0 bits
in DOM1)
(Selected by SS3-0 bits
in DOM1)
APLL
CLK80M
C20i
MTIE_DONE
Frame
Select
MUX
FRAME_A_i
FRAME_B_i
FRAME
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