參數(shù)資料
型號(hào)： ZL50030GAC
廠商： ZARLINK SEMICONDUCTOR INC
元件分類： 路由/交換
英文描述： Flexible 4 K x 2 K Channel Digital Switch with H.110 Interface and 1 K x 1 K Local Switch
中文描述： TELECOM, DIGITAL TIME SWITCH, PBGA220
封裝： 17 X 17 MM, 1.61 MM HEIGHT, PLASTIC, MS-034, BGA-220
文件頁(yè)數(shù)： 8/73頁(yè)
文件大?。?/td> 681K
代理商： ZL50030GAC
ZL50030
Data Sheet
8
Zarlink Semiconductor Inc.
R5, P5, T4, T3,
T2, T1, R4, R3,
R2, R1, P4, P3,
P2, P1
A0 - A13
Address 0 - 13 (5 V Tolerant Inputs).
These are the address lines to the
internal memories and registers.
M2, M1, L3, L1,
L2, K2, K3, K1,
J1, H1, J2, J3,
G1, G3, G2, H2
D0 - D15
Data Bus 0 - 15 (5 V Tolerant I/Os)
. These pins form the 16-bit data bus of
the microport.
H3
DTA
Data Transfer Acknowledge (5 V Tolerant Output)
. This active low output
indicates that a data bus transfer is completed. A pull-up resistor is required
to hold a high level.
B11
PCI_OE
PCI Output Enable (3.3 V Tolerant Input)
. This active low input is the
control signal used to tristate the BSTio0 - 31 pins during hot-swapping.
During normal operation this signal should be low.
P7, R13, T9, T12,
T13
IC_GND
Internal Connection.
These pins
MUST
be connected to ground for normal
operation.
P8, P9, P11, P12,
R8, R9, R10, R11,
R12, T10
IC_OPEN
Internal Connection.
These pins
MUST
be left open for normal operation.
C4, C5, C6, C7,
C8, C9, C10, C11,
C12, C13, D14,
E14, E15, F14,
F15, G14, G15,
H14, H15, J14,
J15, K14, L14,
M6, M7, M8, M9,
M11, M14, N3,
NC
No Connection.
These pins
MUST
be left unconnected for normal
operation.
T7
TDi
Test Serial Data In (3.3 V Input with Internal pull-up)
. JTAG serial test
instructions and data are shifted in on this pin. This pin is pulled high by an
internal pull-up when not driven.
R6
TDo
Test Serial Data Out (3.3 V Tolerant Tri-state Output)
. JTAG serial data is
output on this pin on the falling edge of TCK. This pin is held in high
impedance state when JTAG is not enabled.
T6
TCK
Test Clock (5 V Tolerant Input).
Provides the clock to the JTAG test logic.
This pin should be low when JTAG is not enabled.
R7
TRST
Test Reset (3.3 V Input with Internal pull-up).
Asynchronously initializes
the JTAG TAP Controller by putting it in the Test-Logic-Reset state. This pin
should be pulled low to ensure that the ZL50030 is in normal functional
mode.
T5
TMS
Test Mode Select (5 V-Tolerant Input with Enabled Internal Pull-up)
JTAG signal that controls the state transitions of the TAP controller. This pin
is pulled high by an internal pull-up resistor when it is not driven.
Pin Description (continued)
PBGA
Ball Number
Name
Description
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參數(shù)描述
ZL50030GAG2 制造商:Microsemi Corporation 功能描述:SWIT FABRIC 4K X 2K/1K X 1K 3.3V/5V 220BGA - Trays 制造商:Microsemi Corporation 功能描述:PB FREE FLEX 4KX2K DX+H.110 I/FACE+1K SW 制造商:Zarlink Semiconductor Inc 功能描述:SWIT FABRIC 4K X 2K/1K X 1K 3.3V/5V 220BGA - Trays 制造商:Zarlink Semiconductor Inc 功能描述:PB FREE FLEX 4KX2K DX+H.110 I/FACE+1K SW
ZL50031 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Flexible 4 K x 2 K Channel Digital Switch with H.110 Interface and 2 K x 2 K Local Switch
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ZL50050 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:8 K-Channel Digital Switch with High Jitter Tolerance, Per Stream Rate Conversion (2, 4, 8, 16, or 32 Mbps), and 32 Inputs and 32 Outputs
ZL50050GAC 制造商:Microsemi Corporation 功能描述:8K DX HI JIT TOL, RATE CONV & 32 I/O - Trays
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