參數(shù)資料
型號(hào)： ZL50030GAC
廠商： ZARLINK SEMICONDUCTOR INC
元件分類： 路由/交換
英文描述： Flexible 4 K x 2 K Channel Digital Switch with H.110 Interface and 1 K x 1 K Local Switch
中文描述： TELECOM, DIGITAL TIME SWITCH, PBGA220
封裝： 17 X 17 MM, 1.61 MM HEIGHT, PLASTIC, MS-034, BGA-220
文件頁數(shù)： 42/73頁
文件大小： 681K
代理商： ZL50030GAC
ZL50030
Data Sheet
42
Zarlink Semiconductor Inc.
Figure 14 - Local Output Advancement Timing
Name
Description
LOAn1-0
(See Note 1)
Local Output Advancement Bits 1-0:
These two bits represent the amount of offset
that a particular stream output can be advanced. When the offset is zero, the serial
output stream has normal alignment with the frame pulse.
Note 1: n denotes a LSTio stream number from 0 to 15.
Table 14 - Local Output Advancement Registers (LOAR0 to LOAR1) Bits
Read/Write Addresses:
Reset value:
0020
H
for LOAR0 register,
0000
H
for all LOAR registers.
0021
H
for LOAR1 register,
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
LOAR0 LOA
71
LOA
70
LOA
61
LOA
60
LOA
51
LOA
50
LOA
41
LOA
40
LOA
31
LOA
30
LOA
21
LOA
20
LOA
11
LOA
10
LOA
01
LOA
00
LOAR1 LOA
151
LOA
150
LOA
141
LOA
140
LOA
131
LOA
130
LOA
121
LOA
120
LOA
111
LOA
110
LOA
101
LOA
100
LOA
91
LOA
90
LOA
81
LOA
80
LOAn1
LOAn0
Output
Advancement
2.048 Mbps
(bit)
4.096 Mbps
(bit)
8.192 Mbps
(bit)
0
0
0ns
0
0
0
0
1
- 7.5ns
- 1/64
- 1/32
- 1/16
1
0
- 15ns
- 1/32
- 1/16
- 1/8
1
1
- 22.5ns
- 3/64
- 3/32
- 3/16
C64
8 Mbps Stream
8 Mbps Stream
advancement is 0 ns
LOA=00
advancement is 7.5 ns
LOA=01
Bit 7
Bit 7
8 Mbps Stream
advancement is 15 ns
LOA=10
Bit 7
8 Mbps Stream
advancement is 22.5 ns
LOA=11
Bit 7
denotes the starting point of the bit cell
(internal clock)
ST_FPo0/1
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