- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄373785 > ZL50030GAC (ZARLINK SEMICONDUCTOR INC) Flexible 4 K x 2 K Channel Digital Switch with H.110 Interface and 1 K x 1 K Local Switch PDF資料下載
參數(shù)資料
| 型號： | ZL50030GAC |
| 廠商： | ZARLINK SEMICONDUCTOR INC |
| 元件分類： | 路由/交換 |
| 英文描述： | Flexible 4 K x 2 K Channel Digital Switch with H.110 Interface and 1 K x 1 K Local Switch |
| 中文描述： | TELECOM, DIGITAL TIME SWITCH, PBGA220 |
| 封裝： | 17 X 17 MM, 1.61 MM HEIGHT, PLASTIC, MS-034, BGA-220 |
| 文件頁數(shù)： | 22/73頁 |
| 文件大小： | 681K |
| 代理商： | ZL50030GAC |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁當(dāng)前第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁
ZL50030
Data Sheet
22
Zarlink Semiconductor Inc.
Figure 5 - Typical Timing Control Configuration
15.1.1 Primary Master Mode
In the Primary Master Mode, the ZL50030 drives the “A Clocks” (C8_A_io and FRAME_A_io), by locking to the
primary reference (PRI_REF). The PRI_REF can be provided by one of the locally derived network reference
sources (LREF0-3), the CTREF1 input or the CTREF2 input. In this mode the ZL50030 has the ability to monitor the
primary reference. If the primary reference becomes unreliable, the device continues driving “A Clocks” in stable
Holdover Mode until it makes a Stratum 4 Enhanced compatible switch to the secondary reference (SEC_REF) for
its network timing. The secondary reference can be provided by one of the local network references (LREF0-3),
CTREF1 or CTREF2.
If the primary reference comes back or recovers, the ZL50030 makes a Stratum 4 Enhanced compatible switch
back to the original primary reference and the system returns to normal operation state.
If necessary, the ZL50030 can be prevented from switching back to the original primary reference by programming
the RPS bit in DOM1 register to give preference to the secondary reference.
While in the Primary Master mode, the ZL50030 attenuates jitter and wander above 1.52 Hz from the selected input
reference clock and generates all output clocks according to the DPLL jitter transfer function diagram on Figure 10
on page 31 and Figure 11 on page 32.
For the Primary Master mode selection, see Table 21, "ZL50030 Mode Selection - By Programming DOM1 and
DOM2 Registers" on page 49.
15.1.2 Secondary Master Mode
In the Secondary Master Mode, the ZL50030 drives the “B Clocks” (C8_B_io and FRAME_B_io), by locking to the
“A Clocks”. As required by the H.110 standard, the “B Clocks” are edge-synchronous with the “A Clocks”, as long as
jitter on the “A Clocks” meets Telcordia GR-1244-CORE specifications.
If the “A Clocks” become unreliable, system software is notified and the ZL50030 continues driving the “B Clocks” in
stable Holdover Mode until it makes a Stratum 4 Enhanced compatible switch to the secondary reference
(SEC_REF) for its network timing. The secondary reference can be a local network reference (LREF0-3), CTREF1
or CTREF2. If the “A Clocks” cannot recover, the designated secondary master can be promoted to primary master
by system software. This promotion will cause the “B Clocks” to assume the role of the “A Clocks”.
For the Secondary Master mode selection, see Table 21, "ZL50030 Mode Selection - By Programming DOM1 and
DOM2 Registers" on page 49.
CT_C8_A/CT_FRAME_A
CT_NETREF1
CT_NETREF2
A
Network Ref
(8 kHz / T1 / E1)
PRIMARY
MASTER
CT_C8_B/CT_FRAME_B
B
C
LREF0-3
C
A
B
C
LREF0-3
C
SECONDARY
MASTER
SLAVE
A
B
LREF0-3
N
SLAVE
A
B
LREF0-3
N
Network Ref
(8 kHz / T1 / E1)
Network Ref
(8 kHz / T1 / E1)
Network Ref
(8 kHz / T1 / E1)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ZL50031 | Flexible 4 K x 2 K Channel Digital Switch with H.110 Interface and 2 K x 2 K Local Switch |
| ZL50031QEG1 | Flexible 4 K x 2 K Channel Digital Switch with H.110 Interface and 2 K x 2 K Local Switch |
| ZL50053QCC | 8 K Channel Digital Switch with High Jitter Tolerance, Single Rate (8 or 16 Mbps), and 64 Inputs and 64 Outputs |
| ZL50051 | 8 K Channel Digital Switch with High Jitter Tolerance, Single Rate (8 or 16 Mbps), and 64 Inputs and 64 Outputs |
| ZL50051GAC | 8 K Channel Digital Switch with High Jitter Tolerance, Single Rate (8 or 16 Mbps), and 64 Inputs and 64 Outputs |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ZL50030GAG2 | 制造商:Microsemi Corporation 功能描述:SWIT FABRIC 4K X 2K/1K X 1K 3.3V/5V 220BGA - Trays 制造商:Microsemi Corporation 功能描述:PB FREE FLEX 4KX2K DX+H.110 I/FACE+1K SW 制造商:Zarlink Semiconductor Inc 功能描述:SWIT FABRIC 4K X 2K/1K X 1K 3.3V/5V 220BGA - Trays 制造商:Zarlink Semiconductor Inc 功能描述:PB FREE FLEX 4KX2K DX+H.110 I/FACE+1K SW |
| ZL50031 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Flexible 4 K x 2 K Channel Digital Switch with H.110 Interface and 2 K x 2 K Local Switch |
| ZL50031QEG1 | 制造商:Microsemi Corporation 功能描述:FLEXIBLE 4 K X 2 K CH DGTL SWIT W/ H.110 INTRFC AND 1 K X 1 - Trays 制造商:MICROSEMI CONSUMER MEDICAL PRODUCT GROUP 功能描述:IC DGTL SWITCH 4K X 2K 256MQFP 制造商:Microsemi Corporation 功能描述:IC DGTL SWITCH 4K X 2K 256MQFP |
| ZL50050 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:8 K-Channel Digital Switch with High Jitter Tolerance, Per Stream Rate Conversion (2, 4, 8, 16, or 32 Mbps), and 32 Inputs and 32 Outputs |
| ZL50050GAC | 制造商:Microsemi Corporation 功能描述:8K DX HI JIT TOL, RATE CONV & 32 I/O - Trays |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。