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參數(shù)資料
| 型號： | ZL50030GAC |
| 廠商： | ZARLINK SEMICONDUCTOR INC |
| 元件分類： | 路由/交換 |
| 英文描述： | Flexible 4 K x 2 K Channel Digital Switch with H.110 Interface and 1 K x 1 K Local Switch |
| 中文描述： | TELECOM, DIGITAL TIME SWITCH, PBGA220 |
| 封裝： | 17 X 17 MM, 1.61 MM HEIGHT, PLASTIC, MS-034, BGA-220 |
| 文件頁數(shù)： | 44/73頁 |
| 文件大?。?/td> | 681K |
| 代理商： | ZL50030GAC |
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ZL50030
Data Sheet
44
Zarlink Semiconductor Inc.
Bit
Name
Description
15 - 0
BBER15 -0
Backplane Bit Error Rate Count Bits:
These bits refer to the backplane bit
error count. This counter stops incrementing when it reaches the value 0xFFFF.
Table 18 - Backplane Bit Error Rate Register (BBERR) Bits
Bit
Name
Description
15
CNEN
NREFo Output Enable Bit:
When CNEN is low, NREFo output is disabled, i.e. tri-stated.
When CNEN is high, NREFo output is enabled.
B Clocks Output Enable Bit:
When BEN is low, the “B Clocks” (C8_B_io and FRAME_B_io)
are disabled, i.e. tri-stated - C8_B_io and FRAME_B_io behave as inputs.
14
BEN
When BEN is high, the “B Clocks” are enabled - C8_B_io and FRAME_B_io behave as
outputs.
A Clocks Output Enable Bit:
When AEN is low, the “A Clocks” (C8_A_io and FRAME_A_io)
are disabled, i.e. tri-stated - C8_A_io and FRAME_A_io behave as inputs.
13
AEN
When AEN is high, the “A Clocks” are enabled - C8_A_io and FRAME_A_io behave as
outputs.
Reference Selection Bit:
When RPS is low, the preferred reference is the primary reference
(PRI_REF). When RPS is high, the preferred reference is the secondary reference
(SEC_REF).
SEC_REF Frequency Selection Bits:
These bits are used to select different clock
frequencies for the secondary reference.
12
RPS
11 - 10
FS1- 0
Table 19 - DPLL Operation Mode (DOM1) Register Bits
Read Address: 002A
H
Reset Value: 0000
H
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
BBER
15
BBER
14
BBER
13
BBER
12
BBER
11
BBER
10
BBER
9
BBER
8
BBER
7
BBER
6
BBER
5
BBER
4
BBER
3
BBER
2
BBER
1
BBER
0
Read/Write Address: 002B
H
Reset Value: 0000
H
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
CNEN
BEN
AEN
RPS
FS1
FS0
FP1
FP0
SS3
SS2
SS1
SS0
SP3
SP2
SP1
SP0
FS1
FS0
Secondary Reference
0
0
8 kHz
0
1
1.544 MHz
1
0
2.048 MHz
1
1
8.192 MHz (“A Clocks” or “B Clocks”)
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