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參數(shù)資料
| 型號： | ZL50030GAC |
| 廠商： | ZARLINK SEMICONDUCTOR INC |
| 元件分類： | 路由/交換 |
| 英文描述： | Flexible 4 K x 2 K Channel Digital Switch with H.110 Interface and 1 K x 1 K Local Switch |
| 中文描述： | TELECOM, DIGITAL TIME SWITCH, PBGA220 |
| 封裝： | 17 X 17 MM, 1.61 MM HEIGHT, PLASTIC, MS-034, BGA-220 |
| 文件頁數(shù)： | 7/73頁 |
| 文件大?。?/td> | 681K |
| 代理商： | ZL50030GAC |
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ZL50030
Data Sheet
7
Zarlink Semiconductor Inc.
M16
CTREF2
CT-Bus Reference 2 (5 V Tolerant Input).
This pin accepts 8 kHz,
1.544 MHz or 2.048 MHz network timing reference.
R15, R16, T16,
T15
LREF0 - 3
Local Reference (5 V Tolerant Inputs).
These pins accept 8 kHz,
1.544 MHz or 2.048 MHz local timing reference.
N15
NREFo
Network Reference Output (Output).
Any local reference can be switched
to this output. The output data rate can be either the same as the selected
reference input data rate or divided to be 8 kHz.
N14
PRI_LOS
Primary Reference Lost (5 V Tolerant Input).
When this signal is high, it
indicates that PRIMARY REFERENCE is not valid. Combined with
SEC_LOS input, this input pin is used in the External Reference Switching
Mode of the DPLL.
P13
SEC_LOS
Secondary Reference Lost (5 V Tolerant Input).
When this signal is high,
it indicates that SECONDARY REFERENCE is not valid. Combined with the
PRI_LOS input, this input pin is used in the External Reference Switching
Mode of the DPLL.
P14
FAIL_PRI
Primary Reference Failure (5 V Tolerant Output)
. This pin reflects the
logic status of the PLS bit of the DPLL House Keeping Register (DHKR).
When the primary reference fails, this signal goes to 1.
T14
FAIL_SEC
Secondary Reference Failure (5 V Tolerant Output)
.
This pin reflects the
logic status of the SLS bit of the DPLL House Keeping Register (DHKR).
When the secondary reference fails, this signal goes to 1.
T11
C32/64o
C32/64o Clock (5 V Tolerant Output).
A 32.768 MHz output clock when the
DPLL Clock Monitor register bit (CKM) is low. A 65.536 MHz clock when the
DPLL Clock Monitor register bit (CKM) is high.
R14
C1M5o
C1.5o Clock (5 V Tolerant Output).
A 1.544 MHz output clock.
P16
ST_FPo0
ST-BUS Frame Pulse Output (5 V Tolerant Output).
The width of this
output ST-BUS frame pulse can be 244 ns, 122 ns or 61 ns. The frequency
is 8 kHz.
N16
ST_CKo0
ST-BUS Clock Output (5 V Tolerant Output).
The frequency of this output
ST-BUS clock can be 4.096 MHz, 8.192 MHz or 16.384 MHz.
T8
ST_FPo1
ST-BUS Frame Pulse Output (5 V Tolerant Output)
. The width of this
output ST-BUS frame pulse can be 244 ns, 122 ns or 61 ns. The frequency
is 8 kHz.
P10
ST_CKo1
ST-BUS Clock Output (5 V Tolerant Output)
. The frequency of this output
ST-BUS clock can be 4.096 MHz, 8.192 MHz or 16.384 MHz.
M3
CS
Chip Select (5 V Tolerant Input).
This active low input is used by the
microprocessor to access the microport.
N1
DS
Data Strobe (5 V Tolerant Input).
This active low input works in conjunction
with CS to initiate the read and write cycles.
N2
R/W
Read/Write (5 V Tolerant Input).
This input controls the direction of the data
bus lines (D0 - D15) during the microprocessor access.
Pin Description (continued)
PBGA
Ball Number
Name
Description
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| ZL50030GAG2 | 制造商:Microsemi Corporation 功能描述:SWIT FABRIC 4K X 2K/1K X 1K 3.3V/5V 220BGA - Trays 制造商:Microsemi Corporation 功能描述:PB FREE FLEX 4KX2K DX+H.110 I/FACE+1K SW 制造商:Zarlink Semiconductor Inc 功能描述:SWIT FABRIC 4K X 2K/1K X 1K 3.3V/5V 220BGA - Trays 制造商:Zarlink Semiconductor Inc 功能描述:PB FREE FLEX 4KX2K DX+H.110 I/FACE+1K SW |
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| ZL50031QEG1 | 制造商:Microsemi Corporation 功能描述:FLEXIBLE 4 K X 2 K CH DGTL SWIT W/ H.110 INTRFC AND 1 K X 1 - Trays 制造商:MICROSEMI CONSUMER MEDICAL PRODUCT GROUP 功能描述:IC DGTL SWITCH 4K X 2K 256MQFP 制造商:Microsemi Corporation 功能描述:IC DGTL SWITCH 4K X 2K 256MQFP |
| ZL50050 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:8 K-Channel Digital Switch with High Jitter Tolerance, Per Stream Rate Conversion (2, 4, 8, 16, or 32 Mbps), and 32 Inputs and 32 Outputs |
| ZL50050GAC | 制造商:Microsemi Corporation 功能描述:8K DX HI JIT TOL, RATE CONV & 32 I/O - Trays |
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