參數(shù)資料
型號： ZL50030GAC
廠商： ZARLINK SEMICONDUCTOR INC
元件分類： 路由/交換
英文描述： Flexible 4 K x 2 K Channel Digital Switch with H.110 Interface and 1 K x 1 K Local Switch
中文描述： TELECOM, DIGITAL TIME SWITCH, PBGA220
封裝： 17 X 17 MM, 1.61 MM HEIGHT, PLASTIC, MS-034, BGA-220
文件頁數(shù)： 26/73頁
文件大?。?/td> 681K
代理商： ZL50030GAC
ZL50030
Data Sheet
26
Zarlink Semiconductor Inc.
16.7 Modes of Operation
The DPLL can operate in two main modes: Normal and Holdover Mode. Each of these modes has two states:
primary or secondary state. The state depends on which reference is currently selected as the preferred reference,
PRI_REF or SEC_REF.
16.7.1 Normal Mode
Normal Mode is typically used when a clock source synchronized to the network is required.
In the Normal Mode, the DPLL provides timing (C32/64, CT_C8, C2M and C1M5o) and frame synchronization
(CT_FRAME) signals which are synchronized to one of two input references (PRI_REF or SEC_REF). The input
reference signal may have a nominal frequency of 8 kHz, 1.544 MHz, 2.048 MHz or 8.192 MHz.
From a device reset condition or after reference switch, the DPLL can take up to 50 seconds to phase lock the
output signals to the selected input reference signal.
16.7.2 Holdover Mode
Holdover Mode is typically used for short durations while network synchronization is temporarily disrupted.
If the FDM1-0 bits are programmed to ‘01’ in the DOM2 register and the PRI_LOS and SEC_LOS pins are high, the
DPLL is in the Holdover Mode. The DPLL can also be in the Holdover Mode if the FDM1-0 bits are programmed to
‘00’ and the SLS and PLS bit are observed as ‘11’ in the DPLL House Keeping Register (DHKR).
In the Holdover Mode, the DPLL provides timing and synchronization signals which are based on storage
techniques and are not locked to an external reference signal. The storage value is determined while the device is
in Normal Mode and locked to an external reference signal. When the DPLL is in the Normal Mode and locks to the
input reference signal, a numerical value corresponding to the DPLL output reference frequency is stored
alternately in two memory locations every 32 ms. When the device is switched into the Holdover Mode, the value in
memory from between 32 ms and 64 ms ago is used to set the output frequency of the device.
The frequency stability of the Holdover Mode is
±
0.07 ppm, which translates to a worst case 49 frame (125
μ
s) slips
in 24 hours.
Two factors affect the frequency stability of the Holdover Mode. The first factor is the drift on the frequency of the
master clock (C20i) while in the Holdover Mode. Drift on the master clock directly affects the Holdover Mode
stability. Note that the absolute master clock stability does not affect the Holdover Frequency stability, only the
change in C20i stability while in Holdover. For example, a
±
32 ppm master clock may have a temperature
coefficient of
±
0.1 ppm/
°
C. So a 10 degree change in temperature, while the DPLL is in the Holdover Mode may
result in an additional offset (over the
±
0.07 ppm) in frequency stability of
±
1 ppm, which is much greater than the
±
0.07 ppm of the DPLL. The second factor affecting Holdover frequency stability is large jitter on the reference input
prior to the mode switch.
16.7.3 Freerun Mode
When the DPLL is in the Holdover Mode and the HRST bit of the DOM2 register is pulsed logic high (or held high
continuously), the device is in Freerun Mode.
In Freerun Mode, the DPLL provides timing and synchronization signals which are based on the frequency of the
master clock (C20i) only, and are not synchronized to the reference input signals. The frequency of the output
signals is an ideal frequency with the freerun accuracy of -0.03 ppm plus the accuracy of the master clock (i.e.,
CT_C8 has frequency of 8.192 MHz +/- C20i_accuracy - 0.03 ppm).
Freerun Mode is typically used when a master clock source is required, or immediately following system power-up
before network synchronization is achieved.
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