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參數(shù)資料
| 型號(hào)： | 28F128 |
| 廠商： | Intel Corp. |
| 英文描述： | 3 Volt Intel StrataFlash Memory |
| 中文描述： | 3伏特英特爾StrataFlash存儲(chǔ)器 |
| 文件頁數(shù)： | 32/58頁 |
| 文件大?。?/td> | 380K |
| 代理商： | 28F128 |
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28F128J3A, 28F640J3A, 28F320J3A
26
Preliminary
Table 19. Configuration Coding Definitions
NOTE:
1. When the device is configured in one of the pulse modes, the STS pin pulses low with a typical pulse
width of 250 ns.
4.13
Set Block Lock-Bit Commands
A flexible block locking and unlocking scheme is enabled via block lock-bits. The block lock-bits
gate program and erase operations. Individual block lock-bits can be set using the Set Block Lock-
Bit command. This command is invalid while the WSM is running or the device is suspended.
Set block lock-bit commands are executed by a two-cycle sequence. The set block setup along with
appropriate block address is followed by either the set block lock-bit confirm (and an address
within the block to be locked). The WSM then controls the set lock-bit algorithm. After the
sequence is written, the device automatically outputs status register data when read (see
Figure 12
on page 35
). The CPU can detect the completion of the set lock-bit event by analyzing the STS pin
output or status register bit SR.7.
When the set lock-bit operation is complete, status register bit SR.4 should be checked. If an error
is detected, the status register should be cleared. The CUI will remain in read status register mode
until a new command is issued.
This two-step sequence of set-up followed by execution ensures that lock-bits are not accidentally
set. An invalid Set Block Lock-Bit command will result in status register bits SR.4 and SR.5 being
set to
“
1.
”
Also, reliable operations occur only when V
CC
and V
PEN
are valid. With V
PEN
≤
V
PENLK
, lock-bit contents are protected against alteration.
Reserved
Pulse on
Program
Complete
(1)
Pulse on
Erase
Compete
(1)
bits 7
—
2
bit 1
bit 0
DQ
7
–
DQ
2
= Reserved
DQ
1
–
DQ
0
= STS Pin Configuration Codes
00 = default, level mode RY/BY#
(device ready) indication
01 = pulse on Erase complete
10 = pulse on Program complete
11 = pulse on Erase or Program Complete
Configuration Codes 01b, 10b, and 11b are all pulse mode
such that the STS pin pulses low then high when the
operation indicated by the given configuration is completed.
Configuration Command Sequences for STS pin
configuration (masking bits DQ
7
–
DQ
2
to 00h) are as follows:
Default RY/BY# level mode: B8h, 00h
ER INT (Erase Interrupt): B8h, 01h
Pulse-on-Erase Complete
PR INT (Program Interrupt): B8h, 02h
Pulse-on-Program Complete
ER/PR INT (Erase or Program Interrupt): B8h, 03h
Pulse-on-Erase or Program Complete
DQ
7
–
DQ
2
are reserved for future use.
default (DQ
DQ
= 00) RY/BY#, level mode
—
used to control HOLD to a memory controller to prevent
accessing a flash memory subsystem while any flash device's
WSM is busy.
configuration 01 ER INT, pulse mode
—
used to generate a system interrupt pulse when any flash
device in an array has completed a Block Erase. Helpful for
reformatting blocks after file system free space reclamation or
“
cleanup
”
configuration 10 PR INT, pulse mode
—
used to generate a system interrupt pulse when any flash
device in an array has complete a Program operation. Provides
highest performance for servicing continuous buffer write
operations.
configuration 11 ER/PR INT, pulse mode
—
used to generate system interrupts to trigger servicing of flash
arrays when either erase or program operations are completed
when a common interrupt service routine is desired.
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| 28F128J3A | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:3 Volt Intel StrataFlash Memory |
| 28F128J3A150 | 制造商: 功能描述: 制造商:INTELC 功能描述: 制造商:undefined 功能描述: |
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| 28F128J3FS-12ET | 制造商: 功能描述: 制造商:undefined 功能描述: |
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