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參數(shù)資料
| 型號： | 28F128 |
| 廠商： | Intel Corp. |
| 英文描述： | 3 Volt Intel StrataFlash Memory |
| 中文描述： | 3伏特英特爾StrataFlash存儲器 |
| 文件頁數(shù)： | 44/58頁 |
| 文件大小： | 380K |
| 代理商： | 28F128 |
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28F128J3A, 28F640J3A, 28F320J3A
38
Preliminary
5.0
Design Considerations
5.1
Three-Line Output Control
The device will often be used in large memory arrays. Intel provides five control inputs (CE
0
, CE
1
,
CE
2
, OE#, and RP#) to accommodate multiple memory connections. This control provides for:
a.
Lowest possible memory power dissipation.
b.
Complete assurance that data bus contention will not occur.
To use these control inputs efficiently, an address decoder should enable the device (see
Table 2
)
while OE# should be connected to all memory devices and the system
’
s READ# control line. This
assures that only selected memory devices have active outputs while de-selected memory devices
are in standby mode. RP# should be connected to the system POWERGOOD signal to prevent
unintended writes during system power transitions. POWERGOOD should also toggle during
system reset.
5.2
STS and Block Erase, Program, and Lock-Bit Configuration
Polling
STS is an open drain output that should be connected to V
CCQ
by a pull-up resistor to provide a
hardware method of detecting block erase, program, and lock-bit configuration completion. It is
recommended that a 2.5k resister be used between STS# and V
CCQ
. In default mode, it transitions
low after block erase, program, or lock-bit configuration commands and returns to High Z when
the WSM has finished executing the internal algorithm. For alternate configurations of the STS
pin, see the Configuration command.
STS can be connected to an interrupt input of the system CPU or controller. It is active at all times.
STS, in default mode, is also High Z when the device is in block erase suspend (with programming
inactive), program suspend, or in reset/power-down mode.
5.3
Power Supply Decoupling
Flash memory power switching characteristics require careful device decoupling. System designers
are interested in three supply current issues; standby current levels, active current levels and
transient peaks produced by falling and rising edges of CE
0
, CE
1
, CE
2
, and OE#. Transient current
magnitudes depend on the device outputs
’
capacitive and inductive loading. Two-line control and
proper decoupling capacitor selection will suppress transient voltage peaks. Since Intel StrataFlash
memory devices draw their power from three V
CC
pins (these devices do not include a V
PP
pin), it
is recommended that systems without separate power and ground planes attach a 0.1 μF ceramic
capacitor between each of the device
’
s three V
CC
pins (this includes V
CCQ
) and ground. These
high-frequency, low-inductance capacitors should be placed as close as possible to package leads
on each Intel StrataFlash memory device. Each device should have a 0.1 μF ceramic capacitor
connected between its V
CC
and GND. These high-frequency, low inductance capacitors should be
placed as close as possible to package leads. Additionally, for every eight devices, a 4.7 μF
electrolytic capacitor should be placed between V
CC
and GND at the array
’
s power supply
connection. The bulk capacitor will overcome voltage slumps caused by PC board trace
inductance.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 28F128J3A | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:3 Volt Intel StrataFlash Memory |
| 28F128J3A150 | 制造商: 功能描述: 制造商:INTELC 功能描述: 制造商:undefined 功能描述: |
| 28F128J3A-150 | 制造商: 功能描述: 制造商:undefined 功能描述: |
| 28F128J3D75 | 制造商: 功能描述: 制造商:Intel 功能描述: |
| 28F128J3FS-12ET | 制造商: 功能描述: 制造商:undefined 功能描述: |
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