- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄371435 > 28F128 (Intel Corp.) 3 Volt Intel StrataFlash Memory PDF資料下載
參數(shù)資料
| 型號： | 28F128 |
| 廠商： | Intel Corp. |
| 英文描述： | 3 Volt Intel StrataFlash Memory |
| 中文描述： | 3伏特英特爾StrataFlash存儲器 |
| 文件頁數(shù)： | 31/58頁 |
| 文件大?。?/td> | 380K |
| 代理商： | 28F128 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁當(dāng)前第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁
28F128J3A, 28F640J3A, 28F320J3A
Preliminary
25
4.11.1
Read Configuration
The device will support both asynchronous page mode and standard word/byte reads. No
configuration is required.
Status register and identifier only support standard word/byte single read operations.
Table 18. Read Configuration Register Definition
4.12
Configuration Command
The Status (STS) pin can be configured to different states using the Configuration command. Once
the STS pin has been configured, it remains in that configuration until another configuration
command is issued or RP# is asserted low. Initially, the STS pin defaults to RY/BY# operation
where RY/BY# low indicates that the state machine is busy. RY/BY# high indicates that the state
machine is ready for a new operation or suspended.
Table 19,
“
Configuration Coding Definitions
”
on page 26
displays the possible STS configurations.
To reconfigure the Status (STS) pin to other modes, the Configuration command is given followed
by the desired configuration code. The three alternate configurations are all pulse mode for use as a
system interrupt as described below. For these configurations, bit 0 controls Erase Complete
interrupt pulse, and bit 1 controls Program Complete interrupt pulse. Supplying the 00h
configuration code with the Configuration command resets the STS pin to the default RY/BY#
level mode. The possible configurations and their usage are described in
Table 19,
“
Configuration
Coding Definitions
”
on page 26
. The Configuration command may only be given when the device
is not busy or suspended. Check SR.7 for device status. An invalid configuration code will result in
both status register bits SR.4 and SR.5 being set to
“
1.
”
When configured in one of the pulse
modes, the STS pin pulses low with a typical pulse width of 250 ns.
RM
R
R
R
R
R
R
R
16 (A
16
)
15
14
13
12
11
10
9
R
R
R
R
R
R
R
R
8
7
6
5
4
3
2
1
Notes
RCR.16 = READ MODE (RM)
0 = Standard Word/Byte Reads Enabled (Default)
1 = Page-Mode Reads Enabled
Read mode configuration effects reads from the flash array.
Status register, query, and identifier reads support standard
word/byte read cycles.
RCR.15
–
1 = RESERVED FOR FUTURE ENHANCEMENTS (R)
These bits are reserved for future use. Set these bits to
“
0.
”
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 28F1602C3 | 3 Volt Advanced+ Stacked Chip Scale Package Memory(3V閃速存儲器和靜態(tài)存儲器) |
| 28F3204C3 | 3 V Advanced+ Stacked Chip Scale Package Memory(3V高級堆芯片封裝存儲器) |
| 28F1604C3 | 3 Volt Advanced+ Stacked Chip Scale Package Memory(3V閃速存儲器和靜態(tài)存儲器) |
| 28F160C18 | 1.8V Advanced+ Boot Block Flash Memory(1.8V高級引導(dǎo)塊閃速存儲器) |
| 28F160C2 | 2.4V Advanced+ Boot Block Flash Memory(2.4V高級引導(dǎo)塊閃速存儲器) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 28F128J3A | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:3 Volt Intel StrataFlash Memory |
| 28F128J3A150 | 制造商: 功能描述: 制造商:INTELC 功能描述: 制造商:undefined 功能描述: |
| 28F128J3A-150 | 制造商: 功能描述: 制造商:undefined 功能描述: |
| 28F128J3D75 | 制造商: 功能描述: 制造商:Intel 功能描述: |
| 28F128J3FS-12ET | 制造商: 功能描述: 制造商:undefined 功能描述: |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。