參數(shù)資料
型號: 73M1922-DB
廠商: Maxim Integrated Products
文件頁數(shù): 11/82頁
文件大小: 0K
描述: BOARD DEMO 73M1922 20-TSSOP
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 1
主要目的: *
嵌入式:
已用 IC / 零件: *
主要屬性: *
次要屬性: *
已供物品: 板,CD
DS_1x22_001
73M1822/73M1922 Data Sheet
Rev. 1.6
19
3.3
Serial Interface Timing Specification
The 73M1x22 has a synchronous serial interface, called the MAFE interface, to transfer data to and from a
host. Table 10 provides the timing specification for the MAFE interface.
Table 10: Serial Data Port Timing at 8 kHz Sample Rate
Parameter
Min
Nom
Max
Unit
SCLK period (Tsclk)
1/1.536 MHz
ns
SCLK to
FS delay (td1) – mode1
20
ns
SCLK to
FS delay (td2) – mode1
20
ns
SCLK to SDOUT delay (td3) with 10 pf load
20
ns
Setup time SDIN to SCLK (tsu)
15
ns
Hold time SDIN to SCLK (th)
10
ns
SCLK to
FS delay (td4) – mode 0
20
ns
SCLK to
FS delay (td5) – mode 0
20
ns
Figure 7: MAFE Timing Diagram
3.4
Analog Specifications
This section provides the electrical characterizations of the 73M1x22 analog circuitry.
3.4.1
DC Specifications
VBG is to be connected to an external bypass capacitor with a minimum value of 0.1
μF. This pin is not
intended for any other external use.
Table 11: Reference Voltage Specifications
Parameter
Test Condition
Min
Nom
Max
Units
VBG
VDD=3.0 V – 3.6 V
0.9
1.19
1.4
V
VBG Noise
300 Hz – 3.3 kHz
-86
-80
dBm600
VBG PSRR
300 Hz – 30 kHz
40
dB
FS
(mode1)
FS
(mode0)
SDIN
SDOut
SCLK
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