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參數(shù)資料
| 型號： | 73M1922-DB |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 37/82頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD DEMO 73M1922 20-TSSOP |
| 產(chǎn)品培訓模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標準包裝： | 1 |
| 主要目的： | * |
| 嵌入式： | 否 |
| 已用 IC / 零件： | * |
| 主要屬性： | * |
| 次要屬性： | * |
| 已供物品： | 板，CD |
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73M1822/73M1922 Data Sheet
DS_1x22_017
42
Rev. 1.6
7.3
PLL Prescaler
The prescaler converts the crystal oscillator frequency, Fxtal, to a convenient frequency to be used as a
reference frequency, Fref, for the PLL. A set of three numbers must be entered through the serial port –
PDVSR (5 bit), PRST (3 bit) and PSEQ (8 bit) as follows:
Fxtal
mux
count ctrl
overflow
Counter
Pdvsr
Pdvsr +1
Sequence
Register
Rst
Sequence
Counter
Fref
Pseq]
Prst
Figure 15: Prescaler Block Diagram
PDVSR = Integer [Fref/Fxtal];
PRST = Denominator of the ratio (Fref/Fxtal) minus 1 when it is expressed as a ratio of two smallest
integers = Nnco1/Dnco1;
PSEQ = Divide Sequence
The prescaler should be designed such that the output frequency, Fref, is in the range of 2 ~ 4 MHz.
7.4
PLL Circuit
Figure 16 illustrates a block diagram of the on-chip PLL circuit.
The architecture of the 73M1x22 requires that the PLL output frequency, Fvco, be related to the sampling
rate, Fs, by Fvco = 2 x 2304 x Fs. The NCO must function as a divider whose divide ratio equals Fref/Fvco.
Just as in the NCO prescaler, a set of three numbers must be entered through a serial port to affect this
divide – NDVSR (7 bits), NRST (3 bits) and NSEQ (8 bits) as follows:
NDVSR = Integer [Fref/Fxtal];
NRST = Denominator of the ratio (Fvco/Fref), Dnco1, minus 1, when it is expressed as a ratio of two
smallest integers = Nnco1/Dnco1;
NSEQ = Divide Sequence
VCO
Kvco
NCO
Prescaler
PFD
Charge
Pump
NCO
Kd
Up
Dn
R1
C1
C2
Ichp Control
3
Fref
Kvco Control
PLL output =36.864 MHz
Figure 16: PLL Block Diagram
Upon the system reset, the system clock is equal to Fxtal/9. The system clock will remain at Fxtal until the
host forces the transition no sooner the second Frame Synch period after the write to Register0D. When
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