參數(shù)資料
型號(hào)： 73M1922-DB
廠商： Maxim Integrated Products
文件頁(yè)數(shù)： 40/82頁(yè)
文件大?。?/td> 0K
描述： BOARD DEMO 73M1922 20-TSSOP
產(chǎn)品培訓(xùn)模塊： Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝： 1
主要目的： *
嵌入式： 否
已用 IC / 零件： *
主要屬性： *
次要屬性： *
已供物品： 板，CD
DS_1x22_017
73M1822/73M1922 Data Sheet
Rev. 1.6
45
7.5
PLL System Timing Control
Table 48 describes the registers used for PLL system timing control.
Table 37: PLL System Timing Controls
Function
Mnemonic
Register
Location
Type
Description
PSEQ
0x08[7:0]
W
Sequence of the divisor. If PRST=0, this register is ignored.
PRST
0x09[7:5]
W
Rate at which the sequence register is reset.
PDVSR
0x09[4:0]
W
Divisor value. Default is 01111.
ICHP
0x0A[7:4]
W
The sizes of the charge pump current in the PLL.
KVCOH
0x0A[2:0]
W
The magnitude of KVCO associated with the VCO within PLL.
The following table shows proper KVCOH values per each
desired PLL VOC frequency.
KVCOH2
KVCOH1
KVCOH0
Fvco
Kvco
0
33 MHz
38 MHz/V
0
1
36 MHz
38 MHz/V
0
1
0
44 MHz
40 MHz/V
0
1
48 MHz
40 MHz/V
1
0
57 MHz
63 MHz/V
1
0
1
61 MHz
63 MHz/V
1
0
69 MHz
69 MHz/V
1
73 MHz
69 MHz/V
NDVSR
0x0B[6:0]
W
Divisor value. If NRST=0, this register is ignored.
NSEQ
0x0C[7:0]
W
Divisor sequence.
LOKDET
0x0D[7]
R
Phase Locked Loop Lock Detect
0 = PLL is not locked. (Default)
1 = PLL is locked to PCLK.
CHNGFS
0x0D[3]
W
Sample Rate Change Sequence Enable
0 = No Fs change sequence generated. (Default)
1 = Fs change sequence is enabled.
Setting this bit to 1 minimizes the barrier power loss period
during the sample rate changes. This bit is recommended to
be set to 1 for the applications requiring dynamic sample rate
changes such as V.34 and V.90 modems, etc.
NRST
0x0D[2:0]
W
Represents the rate at which the NCO sequence register is
reset.
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