參數(shù)資料
型號： 73M1922-DB
廠商： Maxim Integrated Products
文件頁數(shù)： 8/82頁
文件大?。?/td> 0K
描述： BOARD DEMO 73M1922 20-TSSOP
產(chǎn)品培訓(xùn)模塊： Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝： 1
主要目的： *
嵌入式： 否
已用 IC / 零件： *
主要屬性： *
次要屬性： *
已供物品： 板，CD
73M1822/73M1922 Data Sheet
DS_1x22_001
16
Rev. 1.6
Pin
Number
Pin Name
Type
Description
14
OSCIN/MCLK
I
Crystal oscillator circuit input pin.
Input from an external clock source. Crystal frequency range
supported is 9 MHz – 27 MHz.
15
OSCOUT
O
Crystal oscillator output pin. (N.C. with external oscillator)
16
VNA/VNPLL
GND
Negative PLL ground
17
VNA
GND
Negative analog ground
18
AOUT
O
Call progress audio output
19
VPA/VPM
PWR
Positive analog supply
20
VNM/VNT
GND
Negative transformer supply
21
M/
S
I
Master or slave selection / reset - active during transition
22
SRE
I
S/Sh regulator sense
23
SRB
O
S/Sh regulator drive
24
VBG
O
VBG bypass, connect to 0.1uF capacitor to VPS
25
ACS
I
AC current sense
26
VNS
GND
LIC analog/digital negative ground
27
VPS
PWR
LIC analog/digital positive supply voltage
28
RXP
I
Receive plus -signal input
29
RXM
I
Receive minus - signal input
30
TXM
O
Transmit minus - signal output
31
DCD
O
DCD for integrated Darlington
32
DCS
I
DC loop current sense
33
DCG
O
DC loop drive
34
DCI
I
DC loop input
35
RGM
I
Ring minus voltage input
36
RGP
I
Ring plus voltage input
37
OFH
O
Off-hook control
38
M20BP
I
Substrate connection. Connect to VNX.
39
VND/VNX
GND
LIC digital/analog negative ground
40
SCP
I/O
Positive side of the secondary pulse transformer winding
41
MID
I/O
Charge pump -normally left open
42
VPX
PWR
LIC supply from the barrier side
2.6
Exposed Bottom Pad on 73M1x66B QFN Packages
The 73M1822 and 73M1922 QFN packages have exposed pads on the underside that are intended
for device manufacturing purposes. These exposed pads are not intended for thermal relief (heat
dissipation) and should not be soldered to the PCB. Soldering of the exposed pad could also
compromise electrical isolation/insulation requirements for proper voltage isolation. Avoid any PCB
traces or through-hole vias on the PCB beneath the exposed pad area.
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