參數(shù)資料
型號(hào)： 73M1922-DB
廠商： Maxim Integrated Products
文件頁(yè)數(shù)： 65/82頁(yè)
文件大?。?/td> 0K
描述： BOARD DEMO 73M1922 20-TSSOP
產(chǎn)品培訓(xùn)模塊： Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝： 1
主要目的： *
嵌入式： 否
已用 IC / 零件： *
主要屬性： *
次要屬性： *
已供物品： 板，CD
73M1822/73M1922 Data Sheet
DS_1x22_017
68
Rev. 1.6
Function
Mnemonic
Register
Location
Type
Description
ACCEN
0x13[4]
W
AC Cancellation Enable
Cancels the AC signals from the DC transconductance circuit.
0 = No AC cancellation. (Default)
1 = Enables the cancellation of AC from the DC transconductance circuit.
This should be set for normal operation.
ENAC
0x12[5]
WO
Enable AC Transconductance Circuit
0 = Shut Down AC Transconductance Circuit. Aux A/D input = Ring
Detect Buffer (RGN) / Line Voltage (DCI). Seize state for going off hook.
(Default)
1 = Enable AC Transconductance Circuit. Aux A/D input = Line Current
(DCS) / Line Voltage (DCI).
ENDC
0x12[6]
WO
Enable DC Transconductance Circuit
0 = Shut down Transconductance Circuit. (Default)
1 = Enable Transconductance Circuit.
ENSHL
0x12[4]
WO
Enable Shunt Loading
0 = Disable shunt loading. (Default)
1 = Enable shunt loading of the line.
ENFEL
0x12[2]
WO
Enable Front End Line-Side Circuit
0 = Power down Front End Line-Side circuits. (Default)
1 = Enable Front End blocks excluding DCGM, ACGM, shunt regulator.
ENLVD
0x12[3]
WO
LeV Detection (OVDT, UVDT, OIDT monitors)
0 = Enable LeV detection. (Default)
1 = Disable LeV detection (used in line-powered mode to save power).
This bit will be 0 when Line Powered Mode is detected (ENLPW is set in
Register 0x02[2]) and set to 1 when an interrupt occurs within the Line-
Side Device. This bit must be reset prior to switching back to Barrier
Powered Mode.
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