參數(shù)資料
型號: 73M1922-DB
廠商: Maxim Integrated Products
文件頁數(shù): 43/82頁
文件大小: 0K
描述: BOARD DEMO 73M1922 20-TSSOP
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標準包裝: 1
主要目的: *
嵌入式:
已用 IC / 零件: *
主要屬性: *
次要屬性: *
已供物品: 板,CD
73M1822/73M1922 Data Sheet
DS_1x22_017
48
Rev. 1.6
SPOS = 0
SPOS = 1
CONTROL FRAMES
DATA FRAMES
Figure 19: Control Frame Position versus SPOS
The SDOUT and
FS pins change values following a rising edge of SCLK. The SDIN pin is sampled on the
falling edge of SCLK.
8.3
Serial Clock Operation
SCLK is a continuous clock running at 256
Fs (Fs = Sample rate frequency). On the 32-pin version of
73M1922, the SCKM (Pin 14), which is weakly pulled high internally, can be connected to ground to stop
the SCLK after 32 clock cycles. This is illustrated in Figure 20.
The 73M1822 and 73M1922 20-pin TSSOP packages only support the continuous SCLK
configuration.
Table 38: Behavior of SCLK under SCKM
SCKM Pin
Number of SCLK Cycles before Being Shut Off
High
Continuous
Low
32
SCLK and
FS in Mode 1 (early FS)
SCLK
FS (Mode1)
32 Cycles of SCLK
SCLK and
FS in Mode 0 (late FS)
FS (Mode0)
SCLK
32 Cycles of SCLK
Figure 20: SCLK and
FS with SCKM = 0
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