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| 型號： | 73M1922-DB |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 57/82頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD DEMO 73M1922 20-TSSOP |
| 產(chǎn)品培訓模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標準包裝： | 1 |
| 主要目的： | * |
| 嵌入式： | 否 |
| 已用 IC / 零件： | * |
| 主要屬性： | * |
| 次要屬性： | * |
| 已供物品： | 板，CD |
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73M1822/73M1922 Data Sheet
DS_1x22_017
60
Rev. 1.6
10.7 Line-Side Device Operating Modes
The architecture of the 73M1x22 is unique in that the isolation barrier device, an inexpensive pulse
transformer, is used to provide power and also bidirectional data between the Host-Side Device and the
Line-Side Device. When the 73M1x22 is on hook, all the power for the Line-Side Device is provided over
the barrier interface. After the Line-Side Device goes off hook, the telco line supplies approximately 8 mA
to the Line-Side Device while the host provides the remainder across the barrier. It is also possible to
power the Line-Side Device entirely from the line provided there is at least 17 mA of loop current available.
Setting the ENLPW bit enables this mode and turns off the power supplied across the barrier. There is a
penalty in using this mode in that the noise and dynamic range are about 6 dB worse than with the Barrier
Powered Mode. It is therefore recommended that the Line Powered Mode be reserved for applications
where the absolute minimum power from the host side is a priority and the reduction in performance can be
tolerated.
Figure 30 shows the AC and DC circuits of the Line-Side Device.
Q5
MMBTA06
1
3
2
U2
73M1912
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
1
2
3
OFH
VND/VNX
SCP
MID
VPX
SRE
SRB
VBG
ACS
VNS
VPS
RXP
RXM
TXM
DCD
DCE
DCB
DCI
RGN
RGP
C23
2.2uF
R18
240
R9
8.2, 1%
R
10
5
.1
K
Q3
MMBTA42
1
3
2
R4 255, 1%
R4
1
00
K
,
1
%
Q6
BCP56
1
2
3
4
RING
-
+
BR1
HD04
4
1
3
2
Q4
MMBTA92
1
3
2
R2
1
0M
R7 5.1K
Q7
MMBTA42
1
3
2
R12
200
R3
4
12
K
,
1
%
TIP
Figure 30: Line-Side Device AC and DC Circuits
The DCVI bits control the voltage versus current characteristics of the 73M1x22 by monitoring the voltage at
the line divided down by the ratios of (R3+R4)/R4 (5:1) during off-hook and (R2+R4)/R4 (101:1) during on-
hook period measured at the DCI pin. This voltage does not include the voltage across the Q4 and the
bridge. When both the ENAC and ENDC bits are set (the hold mode), the DCVI characteristics follow
approximately a 50
Ω load line offset by a factor determined by the DCVI bits. If ENDC=1 and ENAC=0, the
73M1x22 is in the seize mode and the DC voltage characteristic will be reduced to meet the Australian
seize voltage requirements regardless of the setting of the DCVI bits.
10.8 Fail-Safe Operation of the Line-Side Device
The 73M1x22 provides additional protection against improper operation during error and harmful external
events. These include power or communication failure with the Line-Side Device and the detection of
abnormal voltages and currents on the line. The basis of this protection is to ensure that under these
conditions the device is in the On-Hook state and the isolation is provided.
The following events will cause the 73M1x22 Line-Side Device to go to the On-Hook state if it is Off-Hook:
1.
A Power-On Reset occurs while Off-Hook.
2.
The non-transition timer function (see DISNTR) is triggered by the absence of any signal transitions for
more than 400 s on the barrier interface, indicating a problem with communications.
3.
The power supply to the Line-Side Device is below normal operating levels.
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