參數(shù)資料
型號： 73M1922-DB
廠商： Maxim Integrated Products
文件頁數(shù)： 46/82頁
文件大?。?/td> 0K
描述： BOARD DEMO 73M1922 20-TSSOP
產(chǎn)品培訓(xùn)模塊： Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標準包裝： 1
主要目的： *
嵌入式： 否
已用 IC / 零件： *
主要屬性： *
次要屬性： *
已供物品： 板，CD
73M1822/73M1922 Data Sheet
DS_1x22_017
50
Rev. 1.6
8.6
73M1x22 in Daisy Chain Configuration
An internal register controls the daisy chain mode.
FS pin of a slave device is an input from the FSD pin of
the preceding device. In this arrangement, the HC bit (Register 0x02[0]) is ignored and the Software control is
automatically enabled. Setting CTL (bit 0 of the SDIN data stream) to 1 does the control frame request. The
delayed
FS, FSD, is fed to the subsequent slave device as FS. FSD is delayed from FS and always 16 SCLK
periods wide. There are 256 SCLK pulses between frame syncs. A maximum of 7 slaves can be supported.
To aid the host in identifying the master data frame, the least significant bit of the 16-bit word (from SDOUT)
from the master can be forced to “1” and the least significant bit of the 16-bit word from the slave(s) to “0”
by controlling the MSID bits (Register 0x01[2]) of each device. In the cascade mode, the number of slaves
supported must be specified in the NSLAVE bits (Register 0x01[6:4]).
It is important to note that slave devices OSCIN comes from the SCLK pin of the Master device. If a device
is configured as a Slave (M/
S=0), the internal PLL is automatically programmed for the correct operation
regardless of the external PLL programming. Figure 23 and Figure 24 illustrate the daisy chain
configuration.
HOST
SCLK
FSD
FS
OSCIN
SDIN
SDOUT
SCLK
FSD
FS
OSCIN
SDIN
SDOUT
(Slave0)
(Master)
FS
SCLK
SDIN
SDOUT
MCLK
SCLK
FSD
FS
OSCIN
SDIN
SDOUT
(Slave1)
73M1902
73M1822/
73M1902
73M1822/
73M1902
TYPE
M/
S
"1"
MODE
"1"
TYPE
M/
S
"0"
MODE
"x"
TYPE
M/
S
"0"
MODE
"x"
Gray pins are optional depending on the package type.
Figure 23: Daisy Chaining a Master and Two Slaves
FS
128 cycles of sclk
SCLK
FSD(Master)
and
FS(Slave0)
Data Frame
Control Frame
128 cycles of sclk
16 cycles of
sclk
16 cycles of
sclk
If requested by setting the CTL(bit0 of SDIN stream (Master))
16 cycles of
sclk
FSD(Slave0)
and FS(Slave1)
16 cycles of
sclk
Figure 24: Timing Diagram with One Master and Two Slaves
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