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| 型號： | 73M1922-DB |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 44/82頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD DEMO 73M1922 20-TSSOP |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 主要目的： | * |
| 嵌入式： | 否 |
| 已用 IC / 零件： | * |
| 主要屬性： | * |
| 次要屬性： | * |
| 已供物品： | 板，CD |
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DS_1x22_017
73M1822/73M1922 Data Sheet
Rev. 1.6
49
8.4
MicroDAA IN Master/Slave Configuration
The 73M1x22 can be configured as a Slave by resetting the M/
S pin to 0. In this mode, FS of the slave
device(s) becomes an input from
FSD output of the Master or previous slave device. FSD is FS delayed by
16 SCLK cycles. This delay can be adjusted between 16 and 32 by setting the SCK32 bit (Register 0x01[1]
bit for the number of total devices less than or equal to 4. For more slaves, the SCK32 bit should be reset.
This is illustrated in Figure 21 and Figure 22.
FSD is always of Late Type (or “Framed”).
HOST
SCLK
FSD
FS
OSCIN
SDIN
SDOUT
73M1902
SCLK
FSD
FS
OSCIN
SDIN
SDOUT
(Slave)
(Master)
TYPE
M/
S
"1"
FS
SCLK
SDIN
SDOUT
MCLK
73M1822/
73M1902
MODE
"1"
TYPE
M/
S
"0"
MODE
"X"
HOST
SCLK
FSD
FS
OSCIN
SDIN
SDOUT
73M1902
SCLK
FSD
FS
OSCIN
SDIN
SDOUT
(Slave)
TYPE
M/
S
"0"
FS
SCLK
SDIN
SDOUT
73M1822/
73M1902
MODE
"X"
TYPE
M/
S
"0"
MODE
"X"
Note: Gray signals are optional pins depend on package type.
Figure 21: Example Connections for Master and Slave Operation
FS
128 cycles of sclk
SCLK
FSD(Master)
and FS(Slave)
Data Frame
Control Frame
128 cycles of sclk
16 cycles of
sclk
16 cycles of
sclk
if requested by bit0 of SDIN (Slave)
if requested by bit0 of SDIN(Master)
Figure 22: Master/Slave Serial Timing Diagram
8.5
73M1x22 Reset
The 73M1x22 can be initialized to a default state by pulling the
RST pin low for 100 ns or longer. The
device will be ready within 100 μs after the removal of reset pulse. The M/S pin is used to provide reset in
the 73M1822 and 72M1902 20-pin TSSOP packaged parts. The reset signal is also bi-directional and edge
triggered, so either a low-to-high or high-to-low transition will generate a reset. Ensure the final state of M/
S
is the master or slave mode that is desired. M/
S is used as follows:
Slave Mode
Transition the M/
S pin high to low after the power supply has reached the minimum VDD level. If active
reset signal is used on power up, only a high-to-low transition is needed; if a reset is needed after power up,
a low-to-high-to-low toggle of M/
S is used. The serial port should be ignored during this time.
Master Mode
Transition the M/
S pin low to high. The transition from low to high should be after the minimum VDD level is
reached. If an active reset signal is used on power up only a low-to-high transition is needed; if a reset is
needed after power up, a high-to-low-to-high toggle of M/
S is required. The serial port should be ignored
during this time.
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