參數(shù)資料
型號： 73M1922-DB
廠商： Maxim Integrated Products
文件頁數(shù)： 64/82頁
文件大?。?/td> 0K
描述： BOARD DEMO 73M1922 20-TSSOP
產(chǎn)品培訓(xùn)模塊： Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝： 1
主要目的： *
嵌入式： 否
已用 IC / 零件： *
主要屬性： *
次要屬性： *
已供物品： 板，CD
DS_1x22_017
73M1822/73M1922 Data Sheet
Rev. 1.6
67
Function
Mnemonic
Register
Location
Type
Description
FSCTR
0x16[3:0]
W
Filter Sample Rate Selection.
Since impedance matching is done thru the use of a switched capacitor
filter, the realized impedance is exact only if Sample Rate Frequency (Fs)
matches to the Sample Rate specified in FSCTR(3:0). When the actual
sample rate is not any one of the followings in the table, a setting closest
to the actual Fs should be chosen to minimize mismatching errors. These
setting will affect both in AC Impedance Matching Filter (IPMF) and
Receiver Low Pass Notch Filter (RLPN) both.
Control Bits
Fs Assumed (kHz)
FSCTR3 FSCTR2 FSCTR 1 FSCTR 0
IPMF
RLPN
0
7.2
0
1
8
0
1
0
9
9.6
0
1
9.6
0
1
0
10.286
9.6
0
1
0
1
11.2
12
0
1
0
12
0
1
12.8
12
1
0
14.4
1
0
1
16
1
0
1
X
Not allowed
1
X
Not allowed
ACZ
0x17[4:3]
W
Active Termination Loop
Controls the selection of the active termination loops per the table shown
below. ATEN must be set to 1 for selection to be enabled.
ACZ Field
Active Termination Loop Setting
00
600
(Default)
01
270
+ 750 || 150 nF(ETSI ES 203 021-2)
10
200
+ 680 || 100 nF (China)
11
220
+ 820 || 115 nF (Australia)
APWS
0x17[7]
W
Analog Power Save Enable
0 = Saves analog power in LIC of 73M1822 or 73M1912.
1 = Full analog power in LIC of 73M1822 or 73M1912.
RLPNEN
0x16[5]
W
Receive Low Pass Notch Enable
0 = Billing Tone Receive Low Pass Notch (RLPN) filter bypassed.
(Default)
1 = RLPN Filter Enabled. See RLPNH for notch frequency selection.
RLPNH
0x14[2]
W
Receive Low Pass Notch
0 = Selects Receive Low Pass Notch (RLPN) at 12 kHz. (Default)
1 = Selects RLPN at 16 kHz. See RLPNEN at register address 0x16[5] to
enable filter.
THEN
0x15[3]
W
Enable Transhybrid Circuit
The rejection of the transmit signal from the receive signal path.
0 = Transhybrid Circuit disabled. (Default)
1 = Transhybrid Circuit enabled.
This bit should always be set for optimal performance.
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