IDT MIPS32 4Kc Processor Core
Exceptions
79RC32438 User Reference Manual
2 - 48
November 4, 2002
Notes
Entry Vector Used:
General exception vector (offset 0x180)
Execution Exception — Integer Overflow
The integer overflow exception is one of the six execution exceptions. All of these exceptions have the
same priority. An integer overflow exception occurs when selected integer instructions result in a 2’s
complement overflow.
Cause Register ExcCode Value:
Ov
Additional State Saved:
None
Entry Vector Used:
General exception vector (offset 0x180)
Execution Exception — Trap
The trap exception is one of the six execution exceptions. All of these exceptions have the same priority.
A trap exception occurs when a trap instruction results in a TRUE value.
Cause Register ExcCode Value:
Tr
Additional State Saved:
None
Entry Vector Used:
General exception vector (offset 0x180)
Debug Data Break Exception
A debug data break exception occurs when a data hardware breakpoint matches the load/store transac-
tion of an executed load/store instruction. The DEPC register and DBD bit in the Debug register will indicate
the load/store instruction that caused the data hardware breakpoint to match. The load/store instruction that
caused the debug exception has not completed e.g. not updated the register file, and the instruction can be
re-executed after returning from the debug handler.
Debug Register Debug Status Bit Set:
DDBL for a load instruction or DDBS for a store instruction
Additional State Saved:
None
Entry Vector Used:
Debug exception vector
TLB Modified Exception — Data Access
During a data access, a TLB modified exception occurs on a store reference to a mapped address if the
following condition is true:
The matching TLB entry in a TLB-based MMU is valid, but not dirty.
Cause Register ExcCode Value:
Mod
Additional State Saved: