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IDT PCI Bus Interface
PCI Register Description
79RC32438 User Reference Manual
10 - 3
November 4, 2002
Notes
The PCI interface contains six FIFOs. The PCI DMA output FIFO is used for memory to PCI DMA oper-
ations. The PCI DMA input FIFO is used for PCI to memory DMA operations. The IPBus master output
FIFO is used for IPBus master (e.g., CPU) PCI write operations while the IPBus master input FIFO is used
for IPBus master PCI read operations. The PCI target output FIFO is used for external PCI master reads of
the RC32438 local address space while the PCI target input FIFO is used for external PCI master writes to
the RC32438 local address space.
PCI Register Description
FIFO
Size
PCI DMA Output FIFO
64 words
PCI DMA Input FIFO
64 words
CPU Master Output FIFO
4 words
CPU Master Input FIFO
8 words
PCI Target Output FIFO
64 words
PCI Target Input FIFO
64 words
Table 10.1 PCI Bus Interface FIFO Sizes
Register Offset
1
Register Name
Register Function
Size
PCI Bus Interface
0x08_0000
PCIC
PCI control
32-bit
0x08_0004
PCIS
PCI status
32-bit
0x08_0008
PCISM
PCI status mask
32-bit
0x08_000C
PCICFGA
PCI configuration address
32-bit
0x08_0010
PCICFGD
PCI configuration data
32-bit
0x08_0014
PCILBA0
PCI local base address 0
32-bit
0x08_0018
PCILBA0C
PCI local base address 0 control
32-bit
0x08_001C
PCILBA0M
PCI local base address 0 mapping
32-bit
0x08_0020
PCILBA1
PCI local base address 1
32-bit
0x08_0024
PCILBA1C
PCI local base address 1 control
32-bit
0x08_0028
PCILBA1M
PCI local base address 1 mapping
32-bit
0x08_002C
PCILBA2
PCI local base address 2
32-bit
0x08_0030
PCILBA2C
PCI local base address 2 control
32-bit
0x08_0034
PCILBA2M
PCI local base address 2 mapping
32-bit
0x08_0038
PCILBA3
PCI local base address 3
32-bit
0x08_003C
PCILBA3C
PCI local base address 3 control
32-bit
0x08_0040
PCILBA3M
PCI local base address 3 mapping
32-bit
0x08_0044
PCIDAC
PCI decoupled access control
32-bit
0x08_0048
PCIDAS
PCI decoupled access status
32-bit
Table 10.2 PCI Register Map (Part 1 of 2)