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IDT EJTAG System
EJTAG Test Access Port
79RC32438 User Reference Manual
20 - 65
November 4, 2002
Notes
EJTAG Control Register (ECR) (TAP Instruction CONTROL or ALL)
Compliance Level
: Required with EJTAG TAP feature.
The 32-bit EJTAG Control Register (ECR) handles processor reset and soft reset indication, Debug
Mode indication, access start, finish, and size and read/write indication. The ECR also:
–
controls debug vector location and indication of serviced processor accesses,
–
allows a debug interrupt request,
–
indicates processor low-power mode, and
–
allows implementation-dependent processor and peripheral resets.
The EJTAG Control register is not updated/written in the Update-DR state unless the Reset occurred;
that is Rocc (bit 31) is either already 0 or is written to 0 at the same time. This condition ensures proper
handling of processor accesses after a reset. Reset of the processor can be indicated through the Rocc bit
in the JTAG_TCK domain a number of JTAG_TCK cycles after it is removed in the processor clock domain
in order to allow for proper synchronization between the two clock domains. Bits that are R/W in the register
return their written value on a subsequent read, unless other behavior is defined. Internal synchronization
ensures that a written value is updated for reading immediately afterwards, even when the TAP controller
takes the shortest path from the Update-DR to Capture-DR state. Figure 20.32 shows the format of the
EJTAG Control register and Table 20.48 describes the EJTAG Control register fields.
MSB
0
Address
Figure 20.31 Address Register Format
Fields
Description
Read/
Write
Reset
State
Compli-
ance
Name
Bit
Address
MSB:0
Address used by processor access.
R
Undefined
Required
Table 20.47 Address Register Field Description
31
30 29 28
23
22
21
20
19
PRn
W
18
Pr
Acc
17
0
16
Pr
Rst
15
Prob
En
14
Prob
Trap
13
0
12
Ejta
g
Brk
11
0
4
3
2
0
Rocc Psz
0
Doze Halt Per
Rst
DM 0
Figure 20.32 EJTAG Control Register Format