IDT UART Controller
Baud Rate Selection
79RC32438 User Reference Manual
13 - 3
November 4, 2002
Notes
Baud Rate Selection
The baud rate is determined by a two-byte divisor that divides down the IPBus clock (ICLK). The divisor,
in binary, is loaded into the UARTDLL and UARTDLH registers. A divisor value of zero or one is interpreted
as a divisor of 32 decimal (0020 hex) by the baud rate generator.
To calculate the baud rate, use the following formula (the constant, 16, is used in the formula because
the output frequency of the baud rate generator is 16 times the baud):
Baud rate = (system frequency) / (divisor * 16)
Or, to calculate the divisor to load into the Divisor Latches, use the following formula:
Divisor = system frequency / (baud rate * 16)
As an example, for a system frequency of 66 MHz and a baud rate of 9600 (values shown are decimal),
calculate the divisor as follows:
Divisor = 66,000,000 / (9600 * 16) = 429.6875
Round off the ideal divisor to the nearest whole number, 430, to load into the divisor latches. Load
0000_0001_1010_1110 into the divisor latches: 0000_0001 into UARTDLH and 1010_1110 into UARTDLL.
Some divisors and system frequencies will give a more accurate baud rate than others.
To
calculate the percent error
of the divisor, use this formula:
% error =
((difference of the whole divisor and the ideal fractional divisor) / ideal fractional divisor) * 100.
In this example, the error is ((430 - 429.6875) / 429.6875) * 100 = 0.073%. Divisor values for typical
baud rates and system clock frequencies are provided in Table 13.3.
0x05_0028
UART1II (read)
UART1FC (write)
none
UART 1 interrupt identification / UART
1 FIFO control
32-bit
0x05_002C
UART1LC
UART 1 line control
32-bit
0x05_0030
UART1MC
UART 1 modem control
32-bit
0x05_0034
UART1LS
UART 1 line status
32-bit
0x05_0038
UART1MS
UART 1 modem status
32-bit
0x05_003C
UAART1S
UART 1 scratch
32-bit
0x05_0040
UART0RR
UART 0 Reset
32-bit
0x05_0044
UART1RR
UART 1 Reset
32-bit
0x05_0048 through
0x05_7FFF
Reserved
IPBus Clock
Frequency
Baud Rate
Divisor (decimal)
133 MHz
19200
433
116.5 MHz
19200
379
100 MHz
9600
651
66 MHz
19200
214
Table 13.3 Divisor Values for Typical Baud Rates and IPBus Clock Frequencies (Part 1 of 2)
Register
Offset
Register Name
Register Function
Size
DLAB = 0
DLAB = 1
Table 13.2 UART Register Map (Part 2 of 2)